This set of Advanced VHDL Questions and Answers focuses on “Entity and Its Declaration”.
1. Which of the following is not defined by the entity?
a) Direction of any signal
b) Names of signal
c) Different ports
d) Behavior of the signals
Explanation: Entity specifies the name of the entity, the ports of the entity and all the information related to that entity. All designs are created using one or more entities. Declaration of ports in an entity includes the name of signals and there directions.
2. Which of the following can be the name of an entity?
c) Nand gate
Explanation: The name of entity can be basically any name, except VHDL reserved words. NAND is reserved for nand operation and same applies for AND. The name of entity can’t contain any space character. Therefore, only option b is the only legal word.
3. Which of the following is correct syntax for entity declaration?
ENTITY entity_name IS PORT( signal_names : signal_modes; signal_names : signal_modes); END entity_name;
ENTITY entity_name PORT( signal_names : signal_modes; signal_names : signal_modes); END ENTITY;
ENTITY entity_name IS PORT port_name ( signal_names : signal_modes signal_type; signal_names : signal_modes signal_type); END entity_name;
ENTITY entity_name PORT port_name (signal_names : signal_modes; signal_names : signal_modes); END ENTITY;
Explanation: The correct syntax for declaring an entity block starts with reserve word ENTITY followed by name of entity and the next is reserve word IS. Name of entity can contain letters, numbers and underscore character. After this, PORT declaration is used. PORT declaration is used to declare the interface signals for the entity and to assign mode and type of data. The declaration is completed by using END operator and the entity name.
4. Refer to the code given below, how many input output pins are there in MUX entity?
ENTITY mux IS Port ( a,b : IN STD_LOGIC; Y : OUT STD_LOGIC); END mux;
Explanation: In the given declaration, entity has 3 I/O pins. The signals a and b are Input signals and y is the output signal. So, we can say that the declaration is for 2:1 MUX. In this way, we can find the number of I/O pins from the entity declaration.
5. The entity name ‘xyz’ and ‘XYZ’ will be treated same.
Explanation: VHDL is a strongly typed language which means that there are very strict rules regarding the data types. But, there is no difference between names of entity. VHDL is not case sensitive therefore, ‘xyz’ and ‘XYZ’ are same.
6. Which of the following mode of the signal is bidirectional?
Explanation: INOUT is the only bidirectional mode for any signal. IN, OUT and BUFFER are unidirectional mode since they specifies the type to be either input or output. INOUT can be used as both an input to an entity and as an output of the entity. We can read as well as assign the value for INOUT type signal.
7. In an assignment statement, OUT signal can be used only to the ___________
a) Left of <= operator
b) Right of <= operator
c) Any side of <= operator
d) Right of := operator
Explanation: OUT signal is used to take an output from any entity. Therefore, we can assign it any value but can’t read any value from this type of signal. So, in an assignment statement, OUT type signal can be used on the left side of <= operator.
8. On which side of assignment operator, we can use the IN type signal?
d) Can’t be used
Explanation: IN signal is for input only. We can read the value from IN signal. Therefore, it can be placed only on the right side of assignment.
9. What is the difference between OUT and BUFFER?
a) BUFFER can’t be used inside the entity for reading the value and OUT can be
b) BUFFER can only be read whereas OUT can only be assigned a value
c) BUFFER can be read as well as assigned a value but OUT can only be assigned
d) Both are same
Explanation: BUFFER is a unidirectional mode used as an output from the entity. But, the value of BUFFER can be used inside the entity i.e. it can appear on both sides of assignment operator whereas the value of OUT can’t be used inside the entity and can appear on the left side of assignment operator.
10. GENERICs are not declared in the entity.
Explanation: The declaration of GENERICs is also done in the entity itself. It is used to declare the constants that can be used to control the structure of behavior of the entity. The Generics are declared before port declarations.
11. Which of the following is an entity declared for a full adder?
ENTITY full_adder IS PORT(a, b, c : IN BIT; s, co : OUT BIT); END full_adder;
ENTITY full_adder IS PORT (a ,b : IN BIT; s, c : OUT BIT); END full_adder;
ENTITY full_adder PORT(a, b, c : IN BIT; s, co : OUT BIT); END full_adder;
ENTITY full_adder IS PORT (a, b, c, s, co : BIT); END full_adder;
Explanation: A full adder has three inputs and two outputs. Inputs are two bits to be added and some carry. Outputs are sum and carry. Therefore, option a shows the correct declaration of entity full_adder. In this, a and b are the bits to be added and c is the input carry whereas, s is the sum output and co is the carry output.
12. How to control structure and timing of the entity can be changed?
a) By using TIME variable in the entity
b) By changing the entity declaration from time to time
c) By using some special code
d) By using GENERICS
Explanation: The structure and timing constraints can be changed by declaring some constant using GENERICS declaration. For example, in the full adder example, number of bits to be added can be declared as array with its size N. this N can be declared as a constant in the GENERIC declaration part of entity. By changing N only, one can change number of bits for the addition.
13. Which of the following can have more than one driver?
Explanation: INOUT is the only bidirectional signal. This mode can have more than one driver. Therefore, INOUT can be driven by more than one drivers. All other modes like IN, OUT, BUFFER can have only one driver.
14. Which of the following is default mode for a port variable?
Explanation: IN is the default mode for a port variable. If the mode of any signal is not specified in the port declaration, then it is considered as IN type signal. All other types are needed to be specified at the time of declaration.
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