This set of VHDL Multiple Choice Questions & Answers focuses on “LOOP Statement – 2”.
1. The correct syntax for using EXIT in a loop is ___________
a) EXIT loop_label WHEN condition;
b) EXIT WHEN condition loop_label;
c) loop_label WHEN condition EXIT
d) EXIT WHEN loop_label condition
Explanation: EXIT is the keyword used for the execution of EXIT statement. This keyword is followed by the optional loop label which again is followed by keyword WHEN and the condition which should by true for ending the loop. If the loop label is absent, then the exit statement automatically applies tot the innermost enclosing loop.
2. FOR loop uses a loop index, the type of loop index is _________
Explanation: The loop index is used as a counter which counts the number of iterations and this loop index is an INTEGER by default. This is because by using an integer, the counting can be done easily which is not possible with real numbers.
3. Where do we declare the loop index of a FOR LOOP?
d) It doesn’t have to be declared
Explanation: The loop index doesn’t have to be declared because it is always an integer and can be directly used in a loop. So, it is locally declared for a loop. For example, FOR x in 1 TO 10 LOOP; Here ‘x’ is the loop index. Also, it can be reassigned a value within the loop.
4. A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of EXIT statement, the control will be passed ________
a) Outside the FOR loop
b) Outside the WHILE loop
c) At the next iteration of WHILE loop
d) At the next iteration of FOR loop
Explanation: If the loop is nested inside another loop, then exit statement will end the innermost loop only. It will not end the execution of all the loops. It will start execution from the innermost statement containing END LOOP. So, the control will be passed to the statement next to the end of FOR loop.
5. A for loop is initiated as given below, in total how many iterations will be there for the FOR loop?
FOR i IN 0 TO 5 LOOP
Explanation: As told earlier, i is the loop index which is integer by default. So, the counting will start from 0 and then 1 and so on till 5. Therefore, the loop will execute 6 times. If one wants to execute it 5 times then either 0 to 4 or 1 to 5 should be used.
6. All types of FOR loops are synthesizable.
Explanation: The loop index in FOR loop must contain a static value only. It is not possible to synthesize the design if the loop range is not static or it is a variable. So, we can’t use a variable in the loop range line otherwise the loop will not be synthesizable.
7. What is the use of EXIT statement in a loop?
a) For skipping one execution
b) For repeating one statement in the loop
c) For ending the condition and creating infinite loop
d) For ending the loop
Explanation: The exit statement completes the execution of an enclosing loop statement and passes the control to the statement after the exited loop. It will skip all the following iterations and starts execution after the statement containing END LOOP.
8. On what side of the assignment statement, one can use a loop index?
c) Left or Right
d) Loop index can’t be used in an assignment
Explanation: The loop index can be used on the right side of the assignment only. It has read only access. It means that we can’t use index as an output signal. However, it is possible to use this variable as an index to some vector type.
9. A WHILE loop is more flexible than FOR loop.
Explanation: Since we can’t use a signal or variable in the loop range statement, so the FOR loop always runs for a specified or constant number of times. Whereas a WHILE loop can be used to run a loop and we don’t need to know that how many times the loop must be executed.
10. The FOR loop is not synthesizable if it contains ______ statement.
Explanation: The FOR loop is not synthesizable for two conditions. One is That the loop variable must be static. Another condition for the loop to be synthesizable is that it must not contain any kind of WAIT statement.
11. Which logic circuit is described in the following code?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY system IS GENERIC (l : INTEGER := 3); PORT ( a, b : IN STD_LOGIC_VECTOR ( l DOWNTO 0); c : IN STD_LOGIC; x : OUT STD_LOGIC_VECTOR (l DOWNTO 0) y : OUT STD_LOGIC); END system; ARCHITECTURE design OF system IS BEGIN PROCESS (a, b, c) VARIABLE z : STD_LOGIC_VECTOR ( l DOWNTO 0); BEGIN z(0) := c; FOR I IN 0 TO l LOOP x(i) < = a(i) XOR b(i) XOR z(i); z(i+1) <= (a(i) AND b(i)) OR (a(i) AND z(i)) OR (b(i) AND z(i)); END LOOP; y <= z(l); END PROCESS; END design;
a) 4- bit full subtractor
b) 4- bit half subtractor
c) 4- bit half adder
d) 4-bit full adder
Explanation: The design shown in the architecture is the design of 4 bit ripple carry full adder. A generic parameter ‘l’ is used to define the number of bits and for loop is used to describe the data flow of adder. The ‘x’ output is corresponding to the sum output of the adder with 4 bits. Similarly, y output corresponds to the output carry of the adder with one bit only.
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