This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Some Predefined Packages”.
1. Which of the following package need not to be a part of the VHDL code?
Explanation: The package STANDARD is usually integrated directly in the simulation or synthesis program. Therefore, it doesn’t exist as a VHDL description. It doesn’t have to be explicitly included by the USE clause.
2. In which of the following library, the package STANDARD defined?
Explanation: The package STANDARD is a part of STD library which doesn’t need to be included in the code. It is automatically included in the description without any extra statement or declaration. All other packages of STD library needs to be defined in the code itself.
3. Which of the following is not defined in the STANDARD package?
a) Basic data types
b) Functions for different operations for data types
c) Functions to read from the text files
d) Functions for arithmetic operators
Explanation: The package STANDARD contains all the basic data type like Boolean, bit, bit_vector, integer, character and so on. It also contains logical, comparison and arithmetic operators for these data types. It doesn’t contain any function to read and write into text files.
4. Which statement is correct to include a package in the code where we need to read from and write to text files?
a) USE STD.TEXT.all;
b) USE STD.TEXTIO.all;
c) USE IEEE.TEXTIO.all;
d) USE IEEE.TEXT.all;
Explanation: The package which contains procedures and functions needed to read from and write to text files is the TEXTIO package. This package is defined in STD library of the VHDL. So, the correct statement is USE STD.TEXTIO.all to include the TEXTIO package.
5. TEXTIO package is included in the code by default.
Explanation: It is not true that TEXTIO package is included in the code by default. However, it is defined in the STD library from which STANDARD and such packages are included by default but this is not the case with TEXTIO package. It needs the USE clause to be included in the package.
6. Among the four packages given below, which is the most used package of VHDL?
Explanation: The STD_LOGIC_1164 package is most used package in VHDL since it contains definition of data types which are used for modeling wires at the time of synthesis. To use such data types, it is necessary to include STD_LOGIC_1164 in the code. In fact, it is used in almost every single design in VHDL.
7. The STD_LOGIC_1164 package is contained by _______ library.
Explanation: The STD_LOGIC_1164 package has been developed and standardized by the IEEE and hence it is included in IEEE library of VHDL. It could be referenced easily by using two statements: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; Also, this is not included by default.
8. What is the most important use of STD_LOGIC_1164 package?
a) To define and use parallel operations
b) To use concurrent code
c) To use sequential code
d) Multi value logic system
Explanation: STD_LOGIC_1164 defines the data types like STD_LOGIC, STD_ULOGIC and the corresponding vector types. These data types basically work on multi valued logic system rather than two valued logic (0, 1). So, to use this multi value logic we need to include the STD_LOGIC_1164 package.
9. Which package defines the data type STD_LOGIC_SIGNED?
Explanation: SRD_LOGIC_ARITH is another package defined in the IEEE library. This package gives a definition of STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED data types. The basic purpose of STD_LOGIC_ARITH is to provide arithmetic accessibility to STD_LOGIC data types etc.
10. What is another name for STD_LOGIC_ARITH package?
Explanation: STD_LOGIC_ARITH is basically provided by Synopsys and NUMERIC_STD is provided by IEEE. Both of the packages are equivalent and define the same arithmetic functions. So, STD_LOGIC_ARITH is another name for NUMERIC_STD package.
11. The basic arithmetic function provided by STD_LOGIC_ARITH is for ______ data type.
Explanation: STD_LOGIC_ARITH basically contain arithmetic functions to enable calculations and comparisons based on the types STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR. So, calculations related to vector types of STD_LOGIC_1164 are in STD_LOGIC_ARITH package.
12. The following statement must be in _______ package.
TYPE my_type IS RANGE (0, 1);
Explanation: Since the data type my_type can have only two values which are 0 and 1 which is the case of BIT data type. Therefore, my_type is BIT data type which is defined in STANDARD package. So, the given statement must be in STANDARD package.
13. Which of the following package may contain the given statement?
TYPE color IS RANGE (red, green, blue, black)
Explanation: There is no such pre defined data type which may take any value like red, green, blue or black. So, this must be a user defined data type and not a predefined one. Therefore, it must be defined in WORK package.
14. Following lines are a part of _______ package.
TYPE my_type IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘ L’, ‘H’, ‘-‘);
Explanation: The given type shows 9 valued logic which is STD_ULOGIC type having 9 different values. This multi valued logic is defined in STD_LOGIC_1164 package of IEEE library. Apart from STD_ULOGIC, STD_LOGIC is also defined in STD_LOGIC_1164.
15. In STD_LOGIC_1164, the resolution function for ______ is not provided.
Explanation: STD_ULOGIC is the unresolved data type of the STD_LOGIC_1164 package. STD_LOGIC is the resolved version of STD_ULOGIC. Similarly, there are resolution functions to resolve vector types into scalar types.
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