VHDL Questions and Answers – Generics

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Generics”.

1. In which part of the VHDL code, generics are declared?
a) Package declaration
b) Entity
c) Architecture
d) Configurations
View Answer

Answer: b
Explanation: Generics are a general mechanisms used to pass information to an instance of any entity and are declared in the entity itself. These are of constant type and are declared before port declarations. The declaration of generics is followed by the keyword GENERIC.
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2. Which of the following is correct declaration for a generic?
a) GENERIC (name : type := initial_value);
b) GENERIC (type : name := initial_value);
c) GENERIC (name : type <= initial_value);
d) GENERIC ( ype : name <= initial_value);
View Answer

Answer: a
Explanation: The declaration of generic is done in entity declaration part and the correct syntax to declare it is GENERIC ( parameter_name : parameter_type := initial_value). Since, generic is constant object, so := operator is used to assign the initial value.

3. What is the main use of the generic parameter?
a) Defining constant type
b) Assigning some initial value to constant
c) Reusability
d) Using constant type within the entity
View Answer

Answer: c
Explanation: The purpose of defining a generic statement within an entity is to confer more flexibility and reusability. A generic parameter is basically used globally with some value. Whenever one want to reuse same thing again and again then defining it as a generic parameter will be useful rather than defining it again and again.

4. More than one generic parameter can be defined in a single entity.
a) True
b) False
View Answer

Answer: a
Explanation: It is possible to define more than one parameter in an entity. If we want to define more than one generic parameter, then the two parameters must be separated by a semicolon. For example, GENERIC (n : INTEGER := 8; m : BIT_VECTOR := “0011”); In this declaration n and m are two different generics in which one is of INTEGER and another is BIT_VECTOR type.

5. Which of the following is true about Generics?
a) Generics can be assigned information as part of simulation run
b) Generics cannot be assigned information as part of simulation run
c) Generic passes data to an entity which is not instance specific
d) Results of simulation can modify the value of generics
View Answer

Answer: b
Explanation: All the data passed to an entity is instance specific and this data can’t be assigned any information as a part of simulation run. The value of generic is not a simulation specific value but, it is a instance specific value which can’t be modified by the simulation results.
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6. A generic can’t be declared in a component declaration.
a) True
b) False
View Answer

Answer: b
Explanation: A generic can be declared in entity as well as in any component declaration statement. It is not necessary to define generic in entity only. If structural modeling is used, then generic can be used in component declaration statement too. However, it must be noted that the generic is declared before ports declaration.

7. In most synthesis tools, only generics of type ________ are supported.
a) INTEGER
b) REAL
c) BIT_VECTOR
d) STD_LOGIC
View Answer

Answer: a
Explanation: Integer type is the only generics type which is synthesizable in most of the EDA tools. Whereas, in some cases all the types are synthesizable. It is possible to define any type of generic but the thing is that they may not be synthesized.

8. GENERIC (n : INTEGER := 8); In this statement, the mode of generic ‘n’ is _______
a) Integer
b) Real
c) Generic
d) No Mode
View Answer

Answer: d
Explanation: Generics are a means of passing specific information into an entity. Generics can have only a type but no mode. Integer is the type of generic. Mode of any variable or signal defines its direction which means whether it is used as an input signal or output signal. Therefore, mode is not defined in the case of generics.

9. Which function is used to map a generic on design?
a) Port map()
b) Generic()
c) Generic map()
d) Port
View Answer

Answer: c
Explanation: As generic is declared before a port in component and entity declaration. Similarly, to map a generic type, one can use generic map() function before port map() function in component instantiation part of the code. This function is used in structural modeling.
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10. Generics in VHDL can be treated as _______
a) Global variable
b) Local variable
c) Variable
d) Signal
View Answer

Answer: a
Explanation: Generics in VHDL can be taken as global variable which is declared once and is used in complete design. Unlike signals, generics doesn’t have a mode or direction and unlike variable the value of generics can’t be changed.

11. Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?
a) Number of outputs
b) Number of inputs
c) Intermediate signals
d) No parameter
View Answer

Answer: b
Explanation: Generics are used where a single change of value can change it everywhere in the code. For example, if one wants to change the input sizes then it can be changed in entity and respective change is seen everywhere in the code. Since the number of outputs is constant and therefore no need to use number of outputs as generics.

Sanfoundry Global Education & Learning Series – VHDL.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn