This set of VHDL Interview Questions and Answers for freshers focuses on “Operators – 2”.
1. SIGNAL x : STD_LOGIC; In this statement x is ______
Explanation: Identifier is a simple name given to any constant, variable, signal, entity, port or a subprogram. A name must begin with alphabetic letter. It may contain alphanumeric characters and underscore sign. Reserved words of VHDL can’t be used as identifiers.
2. What is the use of shift operators?
a) To shift the data
b) To shift the identifiers
c) To shift the operators
d) To shift the STD_LOGIC_VECTOR
Explanation: Shift operators are used to shifting of data. These operators were introduced in the VHDL93.
3. What is the “SLL” operator?
a) Shift Logic Left
b) Shift Logically
c) Shift Left Logical
d) Shift Left
Explanation: SLL is a shift operator used to shift bits of the operand to one left position and fills the rightmost position with zero. Shift Left Logical(SLL) operator will shift the bits logically. For example, we had data 0100 in the operand, then after applying SLL, we will get 1000.
4. The correct syntax for any logical shift operator like SLL and SRL is_____
a) bit_vector_operand <OPERATOR> integer_operand
b) integer_operand <OPERATOR> bit_vector_operand
c) std_logic_operand <OPERATOR> integer_operand
d) integer_operand <OPERATOR> std_logic_operand
Explanation: SLL and SRL operators can shift the operands of vector type. It may be BIT_VECTOR type or STD_LOGIC_VECTOR type. The left operand is shifted towards left or right depending on the operator with number of shifts represented by right operand which always must be an INTEGER type.
5. Refer to the code given below, what should be the output of the identifier ‘y’ and ‘z’?
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x SRL 2; z := x SLL 2; …
a) y = 0100 and z = 0100
b) y = 0010 and z = 0100
c) y = 0100 and z = 1000
d) y = 0010 and z = 1000
Explanation: SRL operator will shift the operand towards right and SLL will shift the same towards left. All the left bits will be filled with zero in SRL operation and in SLL right bits will be filled with zero. Therefore, y must be x shifted towards right with 2 positions.
6. In the following VHDL code, the values of y and z are _____
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x SRA 2; z := y SLA 2; …
a) y = 0000 and z = 0000
b) y = 1001 and z = 0000
c) y = 1110 and z = 0111
d) y = 0111 and z = 1110
Explanation: SRA and SLA expands to Shift Right Arithmetically and Shift Left Arithmetically respectively. These operators shift the left operand towards right or left by number of bits specified by right operand. Unlike SLL and SRL, the empty bits are not filled with zero, but they are replaced with the MSB in case of SRA and with LSB in case of SLA. For example, in above code, if we shift the x towards right arithmetically then it will become 1100, i.e. the MSB is replicated instead of zero. Therefore, Shifting to two positions will give y = 1110 and z= 0111.
7. SLL operation is equivalent to which of the following operations?
a) Multiplication by any natural number
b) Multiplication by 2
c) Division by 2
d) Exponential operation
Explanation: Shift Left Logical shifts the bits towards left and Shift Right Logical shifts towards right. In binary number system, shifting left refers to multiplication with two and similarly, shifting right refers to division by two. For example, the number 0010 represents 2 in decimal number system. Now, if we shift it left by one position then it will become 0100 which is equivalent to 4 in decimal number system. Therefore, shifting left is equivalent to multiplication operation.
8. Which of the following is equivalent division by 2 operator?
Explanation: SRL operator shifts the given operand towards right. For, example, if we have a number 0010, equivalent to two, which is shifted right then it will become 0001 which is equivalent to 1. Therefore, this operation corresponds to division of any number by two.
9. In the code given below, what will be the values of y and z?
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x ROR 2; z := y ROL 2; …
a) y = 0100 and z = 0000
b) y = 0000 and z = 0000
c) y = 0111 and z = 1110
d) y = 0110 and z = 0110
Explanation: ROR and ROL are Rotate Right and Rotate Left operators respectively. These operators’ wraps around the operand that means the bit shifted out will replace the vacant bit. Therefore, Rotating x two times towards right will give 0110 in y and when it is rotated left then it will be the same.
10. In a statement containing two or more operators of same precedence, how the expression will be solved?
a) Left to right
b) Right to left
d) In a random manner
Explanation: In VHDL, to solve any expression a simple rule is followed. The rule is “highest precedence first, left to right within same precedence”. However, we can use parenthesis to control the order of operations, but by default it will solve left to right. It may be noted that parenthesis is the operator with highest precedence.
11. What will be the values of the following variables after MOD operations?
x = 5 MOD 3; y = -5 MOD 3; z = 5 MOD -3;
a) x = 2, y = -2 and z = -2
b) x = 2, y = 1 and z = -2
c) x= 2, y = -2 and z = 2
d) x = 2, y = -2 and z = 1
Explanation: MOD takes the sign of divisor which is the second operand, but not of first operand. In the first operand, it will simply give the remainder which is 2. In the second statement, the modulo will not contain negative, it will simply divide and the result will be 1. This is done by adding 3*2 in -5, in that case 1 is left, therefore modulo is 1. But, in third statement, divisor is negative so it will be taken as -(5 MOD 3).
12. What will be the values of following variables after REM operations?
x = 5 REM 3; y = -5 REM 3; z = 5 REM -3;
a) x= 2, y = 1 and z = -2
b) x = 2, y = -2 and z = 1
c) x = 2, y = -2 and z = 2
d) x = 2, y = 1 and z = 1
Explanation: Here, REM operator is used, which takes the sign of dividend instead of divisor unlike MOD operator. In case of negative divisor, the sign is ignored. Therefore, in first statement, the remainder is calculated normally, which is 2. In second statement, it will be considered as -(5 REM 3). In third statement, it is simply solved like first statement, ignoring the negative sign.
13. XNOR is a logical operator in VHDL.
Explanation: XNOR is a logical operator representing Ex-NOR operation and was introduced in VHDL 93. In the previous versions, there was no XNOR operator and to perform Ex-NOR, we needed to implement it by using XOR itself.
Sanfoundry Global Education & Learning Series – VHDL.
To practice all areas of VHDL for Interviews, here is complete set of 1000+ Multiple Choice Questions and Answers.