VHDL Questions and Answers – WAIT Statements – 2

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This set of VHDL online test focuses on “WAIT Statements – 2”.

1. Which of the following statement uses only 1 signal?
a) WAIT FOR
b) WAIT UNTIL
c) WAIT ON
d) WAIT UNTIL and WAIT FOR
View Answer

Answer: b
Explanation: In case of WAIT UNTIL statement, there can be more than one condition(using logical operators) but all conditions can use the same signal only. WAIT ON, on the other hand, accepts multiple signals. So, if a process has only one WAIT UNTIL statement then it can be concluded that the process is sensitive to only one signal.
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2. Given that a process has no sensitivity list and has only one WAIT statement which is WAIT FOR statement. How many signals are there to which process is sensitive?
a) 0
b) 1
c) 2
d) Can’t be determined
View Answer

Answer: d
Explanation: It is not necessary that we have to write the time value in WAIT FOR statement. One can also use an expression which will be first solved and then the resulting value will be taken as time value. In that case, we can’t say how many signals are used in the WAIT FOR statement. If the time value is directly given then the process has 0 signals in sensitivity list.

3. WAIT statement provides more flexibility than sensitivity list.
a) True
b) False
View Answer

Answer: a
Explanation: Because the sensitivity list is always written at the starting of the process and this is not true in the case of WAIT statements. They can occur anywhere within the process. Moreover, there can be more than one WAIT statements in the process.

4. Which of the following WAIT statement is most useful for implementing a synchronous sequential circuit?
a) WAIT ON
b) WAIT FOR
c) WAIT UNTIL
d) WAIT TIME
View Answer

Answer: c
Explanation: WAIT ON statement accepts multiple signals whereas WAIT UNTIL statement can have only one signal. In case of the synchronous sequential circuit there is only one clock signal to which the circuit must be sensitive. Therefore, WAIT UNTIL is most suitable for implementing the synchronous circuits.

5. What is the deadlock condition in VHDL?
a) When WAIT statement keeps on waiting forever
b) When WAIT UNTIL statement uses more than one signal
c) When WAIT ON statement has only one signal
d) When WAIT FOR statement doesn’t have any time clause
View Answer

Answer: a
Explanation: Deadlock is a condition where a WAIT statement in a process can wait forever. This can happen when two signals are set by other processes and the condition expression can never be true. This condition is called as deadlock condition. To avoid this ASSERT statement can be used to check the continuity of process.
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6. In case of sensitivity list the process suspends at the end of the process and in WAIT statement it suspends ____________
a) At the beginning
b) At the end
c) At the beginning of architecture
d) Where the WAIT statement is encountered
View Answer

Answer: d
Explanation: WAIT statements are more flexible than sensitivity list and therefore, it can appear anywhere in the process. Wherever the WAIT statement is encountered, the process suspends and waits for any event or condition or a time period depending on the type of WAIT statement. After the condition is met the process continues from the statement next to the WAIT statement.

7. In combinational logic, how many WAIT statements can be used?
a) 0
b) 1
c) 2
d) 3
View Answer

Answer: b
Explanation: However, process is rarely used to implement combinational logic but, sometimes it is required to use WAIT statement. In that case, only one WAIT statement can be there in the process. Otherwise, it can loop forever during initialization.

8. Refer to the code given below, which kind of circuit is implemented?

PROCESS
BEGIN
WAIT on a, b;
z <= a AND b;
END PROCESS;

a) Combinational
b) Synchronous sequential
c) Asynchronous sequential
d) State machine
View Answer

Answer: a
Explanation: Since the process doesn’t contain any clock signal therefore, it can’t be a sequential circuit and hence the process is a combinational circuit. Also, there is only one WAIT statement. Therefore, the design must be a combinational circuit.
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9. In a procedure is called from a process having a sensitivity list, how many wait statement one can use?
a) 3
b) 2
c) 1
d) 0
View Answer

Answer: d
Explanation: In any process with a sensitivity list, there can be no WAIT statements. The same is true for any kind of function or procedure called from the process with sensitivity list. So, in any function or procedure called from a process, we can’t use WAIT statement.

Sanfoundry Global Education & Learning Series – VHDL.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn