VHDL Questions and Answers – Signal vs Variables – 1

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal vs Variables – 1”.

1. Which of the following is the correct use of the signal?
a) To set a default value
b) To pass value between circuits
c) To declare a variable
d) To represent local information
View Answer

Answer: b
Explanation: The signal is a data object which is used to pass a value in and out of the circuit as well as between the internal units of a circuit. Basically, signal represents interconnection of circuits or simply they acts as wires.

2. What is the use of a variable?
a) To represent local value
b) To represent default value
c) To set default value
d) To declare a subprogram
View Answer

Answer: a
Explanation: Variable usually appears inside a block which may be a sequential block like process, function or procedure. It is visible to the corresponding block only. Therefore, variables are used to represent local information.

3. Use of constants is to _________
a) Represent wires
b) Represent local information
c) Represent default value
d) Pass value between entities
View Answer

Answer: c
Explanation: Constant is a data object which serves to establish default value. As the name suggests, the value of constant can’t be modified by using assignment statements. The value is once assigned and the same is used again and again.


4. How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;
View Answer

Answer: a
Explanation: The correct syntax to declare a CONSTANT data object in VHDL is shown in option a. The keyword CONSTANT is followed by the name of the constant which in turn is followed by a colon (:) sign. After the colon sign, the type of constant is specified and the value is assigned by using := assignment operator.

5. Which of the following is local to the block in which it is declared?
a) Signal
b) Integer
c) Constant
d) Variable
View Answer

Answer: d
Explanation: Both Signals and Variables are global to the code whereas Variable is the only data object which is local to the block in which it is declared. For example, a variable x is declared in a process then x will be accessible only within the process.

6. A constant is declared in Architecture, it will be accessible in ________
a) Whole code
b) Within the same architecture
c) In the entity associated and corresponding architecture
d) In the process within the architecture
View Answer

Answer: b
Explanation: A constant when declared in the architecture, it is global to the architecture. That means, no matter how many blocks are there in architecture, the constant can be used in each of those block. Unlike variable which is local to the variable only.

7. Which of the following can’t be declared in an architecture?
a) Signal
b) Constant
c) Variable
View Answer

Answer: c
Explanation: We can’t use a variable data object in architecture directly. Variable is mainly intended for sequential code. So, variables can be declared and used in processes, functions or procedures. However, Signals and variables can be used in architecture.

8. What is the scope of a constant declared in an entity?
a) Local to the entity
b) Global to the whole code
c) Local to the port
d) Global to the entity and all the architecture associated
View Answer

Answer: d
Explanation: The constant declared in an entity can be used in the entity itself as well as the architectures associated with the entity. For example, there are 3 architectures for an entity then all the 3 architectures can access the constant declared in the entity.

9. A user wants a constant to be declared in such a way that it can be accessible by whole code, where should the user declare this constant?
a) Package
b) Entity
c) Architecture
d) Configuration
View Answer

Answer: a
Explanation: When a constant is declared in a package, it is truly global, for the package can be used by several entities and architecture. However, if the same was declared in entity then it can be accessed by the architectures of same entity only.

10. Which of the following is the default type of ports of an entity?
a) Variables
b) Constants
c) Signals
d) Functions
View Answer

Answer: c
Explanation: Since ports of an entity represent the inputs and outputs of a part of the circuit. Therefore, VHDL takes the ports of entity as signals. If no type is specified in front of a port then it will be considered as a signal.

Sanfoundry Global Education & Learning Series – VHDL.

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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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