This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “WAIT Statements – 1”.
1. WAIT statement can’t appear under _______ directly.
a) Architecture
b) Process
c) Procedure
d) Subprogram
View Answer
Explanation: WAIT statement is a sequential statement which is similar to IF statement and its more than one form are available. Since it is a sequential statement, it can appear inside a process, procedure or subprogram, but can’t appear under architecture. In architecture only concurrent statements can be used.
2. Which of the following can’t be used in a process when it has any WAIT statement?
a) IF
b) CASE
c) LOOP
d) Sensitivity list
View Answer
Explanation: One can’t use a WAIT statement along with sensitivity list. It can either have a sensitivity list or some WAIT statements. However, IF, CASE and LOOP are some other sequential statements which can be used when the process has sensitivity list. WAIT statement also contain signals to which the process is sensitive.
3. How many forms of WAIT statement are there in VHDL?
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: There are three forms of WAIT statements among which all of them can be used for synchronous as well as asynchronous sequential code. Some sort of condition or time period is used to stop the execution of process and wait for some event to occur.
4. Which of the following is not the correct WAIT statement?
a) WAIT ON
b) WAIT WHILE
c) WAIT FOR
d) WAIT UNTIL
View Answer
Explanation: WAIT ON, WAIT FOR and WAIT UNTIL are the three types of WAIT signals. There is no WAIT WHILE statement. WAIT ON, FOR and UNTIL are the different types which follow different syntax and different types of WAIT statement which suspends the process for some time.
5. WAIT UNTIL statements cause the process to wait ________
a) When a signal changes value
b) Until a condition is true
c) For a specific time period
d) When either a signal changes its value or a condition comes true
View Answer
Explanation: WAIT UNTIL statement is a form of WAIT statement which causes the process to wait until a condition is true. It is mandatory that the type of condition used must be Boolean. It can be any kind of expression but the result must be of Boolean type.
6. What is the correct syntax for using a WAIT UNTIL statement?
a) WAIT UNTIL boolean_condition_or_expression;
b) WAIT UNTIL signal_name;
c) WAIT UNTIL time_value_or_expression;
d) WAIT UNTIL boolean_expression time_value;
View Answer
Explanation: To write a WAIT UNTIL statement, a Boolean expression is used which causes the process to wait until the expression is true. Unlike IF, CASE and LOOP, the WAIT statement uses a semicolon at the end of the line.
7. What is the use of WAIT FOR statement?
a) To stop execution when the condition is false
b) To stop execution until a signal changes its value
c) To stop execution for a specific time period
d) To stop execution until the clock event occurs
View Answer
Explanation: WAIT FOR statement is useful in the case when we want to suspend the process for a known time period. For example, a delay of 10 ns is used in case of a buffer execution then we can use a WAIT FOR statement.
8. How to define a WAIT FOR statement?
a) WAIT FOR signal_name;
b) WAIT FOR booelan_expression;
c) WAIT FOR clock_event;
d) WAIT FOR time_value;
View Answer
Explanation: WAIT FOR statement can be used by writing the keyword WAIT FOR followed by a time expression. This time expression can be a simple value of time followed by units of time. Since the time is a physical literal of VHDL and its base unit is nanosecond (ns). So, ns is mostly used. For example, WAIT FOR 100 ns; is the correct syntax for WAIT FOR statement.
9. Which of the following is the correct use of WAIT ON statement?
a) To stop execution until a signal changes its value
b) To stop execution when a signal changes its value
c) To stop execution when a condition specified is true
d) To stop execution when a condition specified is false
View Answer
Explanation: The WAIT ON statement puts the process on a hold until any of the signal listed changes its value. This statement is thus useful in detecting the clock events and other similar events. For example, WAIT ON clk will cause the process to wait until a clock event takes place.
10. Which of the following is correct syntax for WAIT ON statement?
a) WAIT ON signal_assignments;
b) WAIT ON boolean_condition;
c) WAIT ON signal_list;
d) WAIT ON time_expression;
View Answer
Explanation: The keyword WAIT is followed by a signal list which is similar to the sensitivity list of the process and the list is used to detect the events. Whenever any signal on the list changes the process resumes the execution.
Sanfoundry Global Education & Learning Series – VHDL.
To practice all areas of VHDL, here is complete set of 1000+ Multiple Choice Questions and Answers.
If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]
- Check VHDL Books
- Practice Electrical & Electronics Engineering MCQs
- Practice Electronics & Communication Engineering MCQs
- Apply for Electrical & Electronics Engineering Internship
- Apply for Electronics & Communication Engineering Internship
