VHDL Questions and Answers – Designing Mealy Type FSM with VHDL

This set of VHDL Puzzles focuses on “Designing Mealy Type FSM with VHDL”.

1. Output values of mealy type FSM are determined by its ________
a) Input values
b) Output values
c) Both input values and current state
d) Current state

Explanation: The output values of a mealy type FSM are determined by its current state and present input values both. Output can change after a change at the inputs immediately, independent of the clock.

2. What kind of output does mealy machine produce?
a) Asynchronous
b) Synchronous
c) Level
d) Pulsed

Explanation: Output of the mealy type FSM is asynchronous it can change in response to any change in the input regardless of the clock. Moore type FSM gives a synchronous output.

3. States in FSM are represented by ________
a) Bits
b) Bytes
c) Word
d) Character

Explanation: Transition states in FSM are represented by bits. The number of bits that are required to represent all the states in FSM is equal to the number of flip-flops required to implement that state machine.

4. What is the first step in writing the VHDL for an FSM?
a) To define the VHDL entity
b) Naming the entity
c) Defining the data type
d) Creating the states

Explanation: The first step in writing the VHDL for an FSM is defining the VHDL entity. The VHDL entity defines the external interface of the system that is being designed, which includes the name of the entity, the inputs and the outputs.

5. A Mealy machine is safer to use.
a) True
b) False

Explanation: Moore machines are safer to use because output changes one cycle later at the clock edge while in mealy machines, input changes the output in the same clock cycle which becomes a problem if two machines are interconnected.
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6. Which of the following react faster to inputs?
a) Sequencer
b) Generators
c) Mealy machines
d) Moore machines

Explanation: Mealy machines react faster to the inputs because they react in the same cycle, they don’t wait for the clock. Moore machines react one cycle later.

7. What is the first state of FSM?
a) Wait loop state
b) Initial state
c) Output state
d) Activate pulse state

Explanation: The first state of the finite state machine is the initial-standby state. It waits until a 1 is read at the input to get started. It then goes to activate pulse state and transmits a high pulse.

8. Mealy machines have _________ states than Moore machine.
a) Fewer
b) More
c) Equal
d) Negligible

Explanation: Mealy machines have fewer states than Moore machine because they respond faster to the input in one cycle only, as they don’t have to wait for the clock. Moore machines generally respond one clock cycle later.

9. Mealy type FSM has a memory element.
a) True
b) False

Explanation: Mealy type FSM has a memory element since it’s a sequential logic system. The past inputs are stored inside the FSM’s memory and represent its state at a given time. The memory elements are the flip-flops.

10. In mealy type FSM, the path is labelled by which of the following?
a) Inputs
b) Outputs
c) Both inputs and outputs
d) Current state

Explanation: In mealy machines, each transition path is labelled with both, the inputs and the outputs and the circle contains the code for the internal state. In Moore machines path is labelled only with the inputs and the circle contains the output and the state code.

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