This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Data Conversion”.

1. Refer to the VHDL code given below, which of the following line has error?

Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line 5: b<=a; Line 6: b<=c;

a) Line 1

b) Line 4

c) Line 5

d) Line 6

View Answer

Explanation: As a is a SIGNAL of BIT type and b is a SIGNAL of std_logic type; so we can’t perform direct operations on these data. For assigning the value of one data type to another data type, we need to use some type of data conversion. Without data conversion, it is illegal. However, line 6 is legal, because STD_LOGIC and my_logic both has same “base”, which means that my_logic is a subset of STD_LOGIC.

2. One can perform basic operations between different data types.

a) True

b) False

View Answer

Explanation: VHDL is a strongly typed language i.e. it has very strict rules about predefined and user defined data types. So, we can’t perform any operation between data of different types. Although, it is possible to perform operation between two data types with same base.

3. How to correctly assign the value of 2x+10 to y in the following VHDL code?

TYPE long IS INTEGER RANGE -1000 TO 1000; TYPE short IS INTEGER RANGE -10 TO 10; SIGNAL x : short; SIGNAL y : long;

a) y <= 2*x + 10;

b) long y <= long 2*x + 10;

c) short y <= long (2*x + 10);

d) y <= long (2*x + 10);

View Answer

Explanation: For all the data types with same base, the conversion can be carried out at the time of operation itself. Therefore, if we want to assign a value of ‘short’ type to a variable of ‘long’ type; we may simply write ‘long’ just after the assignment operator. By doing so, user can convert one type into another. Note that, it is only possible if and only if both the types are having same base.

4. In the VHDL code given below, what will be the error at the time of compilation?

TYPE my_int IS INTEGER RANGE -32 TO 32; TYPE other_int IS INTEGER RANGE 0 TO 100; SIGNAL x : my_int; SIGNAL y : other_int; y <= x + 2; …

a) Type mismatch

b) Syntax problem

c) No declaration

d) Can’t compile

View Answer

Explanation: Here, we have two user defined data types which are my_int and other_int with the same base. But, we can’t directly perform any operation between the signals of these two different types. Such kind of error is called “Type Mismatch” error. First, user needs to convert my_int to other_int. so, the correct assignment statement will be:- y<= other_int (x + 2);

5. Which of the following package of IEEE contains most of the data conversion functions?

a) std_logic_1164

b) std

c) std_logic_arith

d) std_logic

View Answer

Explanation: Most of the conversion functions are defined in the std_logic_arith package of IEEE library. When user need to convert one type of data into another type and both have different bases, then it is essential that he/she need to declare the std_logic_arith package in the library declaration part. However, when we need to convert the data types with same base, then the functions are defined in std_logic_1164 package.

6. If we are using conv_integer(p) function, then which of the following cannot be the type of parameter ‘p’?

a) STD_LOGIC VECTOR

b) STD_ULOGIC

c) INTEGER

d) SIGNED

View Answer

Explanation: The function conv_integer(p) is used to convert the parameter ‘p’ of any type excluding STD_LOGIC_VECTOR into the integer type. This function can covert INTEGER, SIGNED, UNSIGNED, STD_ULOGIC types into integer type. After converting only, we can use ‘p’ as INTEGER type.

7. In the function conv_unsigned(p, b), what does p and b refers to?

a) p is the data object to be converted and b is the base of that data object

b) p is the data object to be converted amd b is the bits needed in converted variable

c) p is the parameter to be converted and b is the bits of same parameter

d) p is the type of data to be converted and b is the type of data into which p should be converted

View Answer

Explanation: The function conv_unsigned is used to convert different data types in UNSIGNED type. Two arguments are used in this function which are p and b. p is the data object which we need to convert and b represents the no of bits in UNSIGNED type. So, conv_unsigned(p,b) converts the parameter ‘p’ of INTEGER, SIGNED, UNSIGNED, STD_ULGOIC into UNSIGNED type of size ‘b’ bits.

8. Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?

a) conv_integer_signed(p,b);

b) conv_signed_integer(p,b);

c) conv_signed(p,b);

d) conv_signed_p(b);

View Answer

Explanation: To convert INTEGER, SIGNED, UNSIGNED and STD_ULOGIC types into SIGNED type, the function conv_signed is used. The correct way to use this function is :- conv_signed(p,b) where p is the object to be converted and b is the number of bits in SIGNED type.

9. The function conv_std_logic_vector(p,b) is used for_______

a) Converting ‘p’ form STD_LOGIC_VECTOR to STD_LOGIC type

b) Converting any data type ‘p’ into STD_LOGIC_VECTOR with ‘b’ bits

c) Converting STD_LOGIC_VECTOR into ‘p’ type with ‘b’ bits

d) Converting STD_LOGIC into STD_LOGIC_VECTOR

View Answer

Explanation: This function is used to convert the parameter ‘p’ of type INTEGER, UNSIGNED, SIGNED or STD_LOGIC into STD_LOGIC_VECTOR. Note that the size of converted variable will be ‘b’ bits. So, b represents the number of bits in the converted object.

10. What will be the value of y after the execution of the following VHDL code?

Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL m : UNSIGNED (3 DOWNTO 0); SIGNAL n : UNSIGNED (3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0); y <=CONV_STD_LOGIC_VECTOR ((m+n), 8); …

a) 8- bit STD_LOGIC_VECTOR m+n

b) 8- bit UNSIGNED m+n

c) 4- bit STD_LOGIC m+n

d) Error

View Answer

Explanation: Here, the conversion function is used to convert the data objects into STD_LOGIC_VECTOR type. The operation ‘m+n’ is completely legal since both are UNSIGNED type, after this operation the result is converted into STD_LOGIC_VECTOR with size ‘8’ bits. So, the values assigned to ‘y’ will be of STD_LOGIC_VECTOR type of 8 bits.

11. Refer to the VHDL code given below, what will be the output?

Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL a : IN INTEGER; SIGNAL b : IN UNSIGNED (3 DOWNTO 0); SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); y <<=CONV_STD_LOGIC_VECTOR ((a+b), 8); …

a) 8- bit STD_LOGIC_VECTOR a+b

b) 8- bit UNSIGNED a+b

c) 4- bit STD_LOGIC_VECTOR a+b

d) Error

View Answer

Explanation: The code is not completely legal. There will be an error of type mismatch. Since a and b are two completely different data types, one is INTEGER and another is UNSIGNED. So, we can’t perform the operation ‘a+b’. Therefore, to perform this operation, first a and b need to be of same type, which can be done by converting INTEGER into UNSIGNED or vice-versa.

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