This set of VHDL Quiz focuses on “Process Statement – 2”.
1. It is possible to use sensitivity list and wait statements in the same process.
Explanation: The sensitivity list and wait statements can’t be used simultaneously in the same process. One can either use sensitive list or wait statements in a process. Both of them are used to define the signals to which the process is sensitive. These sensitive signals execute process as an infinite loop.
2. The process can be __________ by using WAIT statements.
c) Suspended as well as resumed
d) Cannot be determined
Explanation: The signals used in WAIT statements are the statements which can also be declared in sensitivity list. These signals can be used to suspend as well as resume the process as many times as designer want.
3. A postponed process runs when ___________
a) All the other processes have completed
b) After completion of one particular process
c) Concurrently with all other processes
d) First of all processes
Explanation: A postponed process can be defined in VHDL-93. A postponed process runs when all the normal processes have completed at a particular point of time at the time of simulation. These processes can’t schedule any further events with zero delay.
4. Which of the following statement can’t be used inside a process?
b) IF ELSE
c) Variable declaration
d) PORT MAP
Explanation: A process itself is a concurrent statement which can have only sequential statements. IF ELSE and WAIT statements can be easily used inside a process. Also, there is a declaration part of the process so variable declaration is possible. Only PORT MAP is not possible inside the process among the above options since it is a concurrent statement.
5. Which of the following signal cause the process to execute?
PROCESS (clr) BEGIN IF (clr = ‘1’) THEN y <= ‘0’; ELSE y <= input; END PROCESS;
Explanation: The sensitivity list of process contains only one signal which is ‘clr’. So, the process will be executed when the value of clr changes. Though value of input will be assigned to y once but change in value of ‘input’ will not cause execution of process again.
6. The value of y is initially 1 and it is changed after one delta cycle to 0. How many delta cycles (starting from the beginning) will be taken to change the initial value of z, refer to the process given below?
PROCESS (y) BEGIN x <=y; z <= NOT y; END PROCESS
Explanation: At the very beginning, the value of z is 0. After 1 delta cycle, the value of y changes which causes process to run again. So, in 2nd delta cycle process will be executed but assignments will be done after the execution of process is over. So, at the end of 2nd delta cycle, the assignments will be executed.
7. A combinational process must have all the _________ signals in its sensitivity list.
Explanation: All the inputs must be used in the sensitivity list to get the desired list. Because if any of the input signal is updated then it is needed that the output also gets updated. To update any output, one needs to activate the process again which is possible only by the signals in the sensitivity list. Therefore, all the signals which it has to read or the input signals must be used in the sensitivity list.
8. There is no restriction on the number of wait statements inside a process.
Explanation: A process can have multiple WAIT statements and can be placed anywhere inside the process body. However, it can have only one sensitivity list (can contain many signals) but, there is no restriction on use of WAIT statements.
9. Which of the following circuit can’t be described without using a process statement?
b) D flip-flop
Explanation: Since a flip flop requires a clock signal which can’t be used directly in architecture without using a process (as it is a sequential process). So, for using the clock, using a process is mandatory. All the other circuits like multiplexer, decoder or comparator are combinational circuits and do not need any clock. So, they can be modeled without using a process.
10. Which of the following signal uses keyword EVENT?
Explanation: To use a clock signal in a design description, EVENT is used. It is used inside the process body which indicates the change in value of clock signal so that the design can be synchronized with the clock signal or clock frequency. It can be used in an IF statement to assign any input expression to the output.
11. Refer to the code given below, what kind of circuit is designed?
SIGNAL x : IN BIT; SIGNAL y : OUT BIT; SIGNAL clk : IN BIT; PROCESS (clk) BEGIN IF (clk’EVENT and clk = ‘1’) y ;<= x; END PROCESS
c) Flip flop
d) Shift Register
Explanation: It is clear from the code that it is a sequential circuit using clock EVENT and the value of input is assigned to the output directly. So, it can’t be a buffer since buffer doesn’t need any clock signal. So, It is a synchronized flip flop. Clearly, It can be said that the given flip flop is a D flip flop.
12. The driver(s) of signal y is _________
PROCESS () BEGIN y <= ‘1’; y <= x; y <= z; END PROCESS;
c) x and z
Explanation: Since the assignment statements are appearing inside a process. Therefore, they are sequential assignment statement. A signal being assigned a value inside a process can’t have multiple drivers. It can have only one driver since only last statement is taken into consideration. So, the signal y is driven by signal z.
13. The resolution function is needed to resolve the value of _______
PROCESS () BEGIN y <= x; y <= z; END PROCESS;
d) No x, y and z
Explanation: Since these assignments are appearing inside a process so no signal can have more than one driver. A resolution function is needed only if the signal has multiple drivers. However, if these statements were used outside the process, then the resolution function was required to resolve the value of y.
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