This set of VHDL Interview Questions and Answers focuses on “Data Objects and Types”.
1. SIGNED and UNSIGNED data types are defined in which package?
a) std_logic_1164 package
b) std_logic package
c) std_logic_arith package
d) standard package
Explanation: SIGNED and UNSIGNED data types are defined in std_logic_arith package of the ieee library. These data types are mainly intended for arithmetic operations. This is why they are defined in arithmetic package.
2. What is the correct method to declare a SIGNED type signal ‘x’?
a) SIGNAL x : IN SIGNED
b) SIGNAL x : IN SIGNED
c) SIGNAL x : IN SIGNED (7 DOWNTO 0 )
d) SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0 )
Explanation: Unlike BIT and STD_LOGIC types; SIGNED and UNSIGNED follow the syntax similar to BIT_VECTOR and STD_LOGIC_VECTOR. Also, IN and OUT are just to specify the direction of signal.
3. An UNSIGNED type is always greater than zero.
Explanation: In SIGNED and UNSIGNED, SIGN word refers to the positive or negative sign of any number. UNSIGNED data type has no sign and therefore, it is always positive. Therefore, an UNSIGNED number will be always greater than zero.
4. What will be the value of x in the following code?
SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;
Explanation: x is declared as an UNSIGNED data type. Therefore, all the 4 bits will be data bits and it will be positive. So, converting 1101 in decimal, we get 1101 equivalent to 14 in decimal number system.
5. What is the decimal equivalent of x in the following code?
SIGNAL x : OUT SIGNED (3 DOWNTO 0 ); x <= “1101”;
Explanation: Signed numbers always have first bit representing the sign of the number which is one for the negative and zero for the positive. Also, signed number is represented in 2’s complement form. Therefore, the given number is -3.
6. Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?
a) x <= a + b; y <= a – b;
b) x <= a OR b; y <= a AND b;
c) x <= a + b; y <= a OR b;
d) x <= a OR b; y <= a + b;
Explanation: SIGNED and UNSIGNED data types are intended for arithmetic operations mainly and using logical operators with these data types is illegal. Therefore, only option a is completely legal. In all other options there are logical operations so those can’t be considered as legal.
7. If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is
a) x <= a.b
b) x <= a OR b
c) x <= a + b
d) x <= a && b
Explanation: Unlike SIGNED and UNSIGNED, STD_LOGIC_VECTOR data type is used mainly for logical operations and we can’t use arithmetic operations with STD_LOGIC_VECTOR. Also, && is not the sign for any operation in VHDL, if you want to perform and operation, then you have to write AND not &&.
8. What do we call the data type used for representing distance, current, voltage, time etc?
Explanation: Physical type is used for representing physical values such as time, voltage etc. by using some base unit. Physical quantities are used in various digital systems and these are important for modelling such systems. Integer and Real are the data types for numbers and there is no data type called Imaginary.
9. What is the meaning of base unit?
a) Smallest possible unit of any physical literal
b) SI unit of any physical literal
c) CGS unit for any physical literal
d) Fundamental building block of any design
Explanation: Base unit is the smallest possible unit for any physical literal by using which we can derive all other units of the same literal. For example, in case of TIME, the base unit is nanosecond. We can create any bigger unit by using nanoseconds. For example 1 microsecond = 1000 nanosecond.
10. Which of the following is only predefined physical literal in VHDL?
Explanation: TIME is the only predefined physical data type in VHDL. The base unit of TIME is nanosecond. TIME literal is defined in the standard package of std library.
11. SIGNAL a : REAL; which of the following is illegal assignment for a?
a) a <= 1.8
b) a <= 1.0 E10
c) a <= 1.0 E-10
d) a <=1.0 ns
Explanation: Units nanosecond (ns) written after the number shows that it is of type TIME and VHDL doesn’t allow TIME type to be assigned to a real Signal. So option d is illegal.
12. Multidimensional arrays can be used for the implementation of memories.
Explanation: Multidimensional arrays can be seen as array of arrays. For example, we need to implement ROM of 512×4 then we need to define a 2 dimensional array with 4 columns and 512 rows. So, memories can be defined by using 2D array. In which one dimension can show the size of memory and another can show the width of one word.
13. RECORD in VHDL is similar to________ in C.
Explanation: As in C, Structures are used to collect different data types under a common name. Similarly, RECORD type in VHDL is used for collecting different data types and objects in a single object.
14. What is the difference between SIGNAL and VARIABLE?
a) The value of SIGNAL never varies whereas VARIABLE can change its value
b) SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals
c) SIGNAL depends upon VARIABLE for various operations
d) SIGNAL is global and VARIABLE is local to the process in which it is declared
Explanation: SIGNALs are used to pass information between entities, they acts as interconnection between different entities whereas VARIABLEs can be used in the process or subprogram in which it is declared. So, VARIABLEs are local to the block in which they are declared.
15. Access types are similar to _________ in traditional programming languages.
Explanation: Access types are used to hold an address of some object which is quite similar to pointers in traditional programming languages. By using the address stored in Access data type, we can access another data objects similar to pointers.
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