# VHDL Questions and Answers – Designing Counters with VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing Counters with VHDL”.

1. The ring counter is a serial shift register with feedback from the output of the last flip-flop to the input of the first flip-flop.
a) True
b) False

Explanation: Ring counter is a serial shift register based on continuous circulation. Feeding back the output of the serial shift register to its input without inversion creates a circuit.

2. Which of the following flip-flop is used by the ring counter?
a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops

Explanation: Ring counter comprises of a few single bit D flip-flops, one flip-flop for one data bit, either a logic 1 or a 0. They are connected together to form a sequence so that the output from the first flip-flop becomes the input of the second flip-flop and so on.

3. ‘shift_reg’ is used to initialize the _____________ in the shift register.
a) LSB
b) MSB
c) Register type
d) Register bits

Explanation: Shift register uses ‘shift_reg’ for the initialization. It sets the value of MSB in the shift register with the following code:
(signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := X”80″;)

4. How many types of shift operators are there in VHDL?
a) Three
b) Four
c) Five
d) Six

Explanation: There are six types of shift operators in VHDL: rol (rotate left logical), ror (rotate right logical), sll (shift left logical), srl (shift right logical), sla (shift left arithmetic), sra (shift right arithmetic).

5. How many types of the data type are there in the ring counter?
a) One
b) Two
c) Three
d) More than three

Explanation: There are more than three data types in VHDL, some of them are: STD_LOGIC_VECTOR data type – for more than one bit, the STD_LOGIC data type – for a single bit, the BIT_VECTOR data type – for two or more bits, STD_LOGIC_UNSIGNED data type – for addition and subtraction.
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6. In __________ counter universal clock is not used.
a) Synchronous counter
b) Asynchronous counter
d) Ring counter

Explanation: In asynchronous counter, the universal clock is not used, only the first flip-flop is operated by the main clock and output of the previous flip-flops operates the clock input of the rest of the counters.

7. Synchronous counter use ________ global clock, unlike asynchronous counter.
a) One
b) Two
c) Three
d) zero

Explanation: Synchronous counter use one global clock that operates each flip flop and changes the output in parallel. One advantage of the synchronous counter as compared to asynchronous counter is, it can work on a much higher frequency than the asynchronous counter.

8. Asynchronous counters are generally used in circuits with higher frequency, where a large number of bits are involved.
a) True
b) False

Explanation: In asynchronous counters, there are small delays between the arrival of the clock pulse at the input due to the internal circuit of the gate so, if the delay of the all the stages are added together the total delay at the end of the counter can be very large. Therefore, asynchronous counters are not used in high-frequency circuits where large numbers of bits are involved.

9. How many different states does a decade counter count?
a) Eight
b) Nine
c) Ten
d) Eleven

Explanation: Ten different states are counted by a decade counter. It then resets to its initial state. A simple decade counter counts from 0 to 9. Also, counters could be made which can go through any ten states between 0 to 15.

10. The number of flip-flops used in a counter is _________ number of states in the counter.
a) Greater than
b) Less than
c) Equal to
d) Greater than equal to

Explanation: Number of flip-flops used in a counter is greater than equal to the number of states in the counter. It can be calculated by using ‘log2 n’ where n=number of states in the counter.

11. Two decade counters cascaded together will divide the input frequency by ________
a) 10
b) 100
c) 1000
d) 10000

Explanation: A decade counter has 10 states, so it divides the input frequency by 10. Two decade counters will divide the input frequency by 10*10=100.

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