This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Block Statement”.
1. What do you mean by a block?
a) An object of architecture
b) Interconnection of two or more signals
c) A part of an entity
d) A sub module in an architecture body
Explanation: The sub modules in architecture can be described as blocks. A block is a unit of module structure, with its own interface, connected to other blocks or ports. For example, while designing CPU, one can divide the architecture into blocks in which one may be describing ALU and another may be describing Control signals and so on.
2. Which of the following is correct syntax for block definition?
label : BLOCK declarative_part; BEGIN concurrent_statements; end BLOCK label;
label : BLOCK declarative_part; BEGIN concurrent_statements; end label BLOCK;
BLOCK block_name; declarative_part; BEGIN concurrent_statements; end BLOCK block_name;
BLOCK block_name declarative_part; BEGIN sequential_statements; end BLOCK;
Explanation: A block is declared by using some label. First, a label is given to the block which is followed by a colon and then the keyword BLOCK. In the next line, signals, components, constants etc. are declared. After the declaration part of the block, BEGIN keyword is used followed by concurrent statements describing the behavior of the block.
3. What is the scope of variables or signals declared in the block statement?
a) Global to the design
b) Local to the architecture
c) Local to the block itself
d) Local to the entity of which architecture is defined
Explanation: The variables or signals declared in the BLOCK are available local in the block statement only. However, a block can declare constants, types, components, subprograms apart from variables or signals. But, anything declared in the block can be used in the block only.
4. Which of the following defines the interface to the block?
a) Block declaration part
b) Block header
c) Block statement part
d) Generic declaration part
Explanation: A block header defines the interface to an entity. The values of generics or components associated with the block are defined in the block header. It uses a port map and generic map functions to declare and map components and generics with the block.
5. Guarded block has an extra ________ expression.
Explanation: VHDL has two types of block which are Simple blocks and guarded blocks. Guarded blocks have an extra guard expression. The role of guard expression is to control the execution of guarded block. The guarded statements in a guarded block are executed only when the guard expression is TRUE.
6. What should be the type of the value of guard expression?
Explanation: The type of result of guard expression should be BOOLEAN which may take only two values either TRUE or FALSE. The statements under guarded block are executed only when the result of guard expression is TRUE. Therefore, it is mandatory to have an expression with BOOLEAN output.
7. What is the main purpose of using blocks?
a) To improve reusability
b) To improve conditional execution
c) To improve readability
d) To improve speed of execution
Explanation: Blocks are useful to improve the readability and management of VHDL design. In a high level design, say CPU design, blocks are very useful since it can be divided into blocks which can further be managed easily rather than managing whole code. Another use of block statement is to disable some signals by using guard expression. However, the result of simulation will be same of the code using block and the same without blocks.
8. Guarded blocks are synthesizable.
Explanation: In general EDA tools, the guarded blocks are not synthesizable and unguarded blocks doesn’t add any additional functionality to the design and therefore, are usually ignored by synthesis tools. So, it is not much useful to use blocks in non-VITAL designs.
9. Which of the following is better for design partitioning?
a) Guarded block
b) Unguarded block
c) Component instantiation
d) Component declaration
Explanation: Since guarded and unguarded blocks are not synthesizable. So, component instantiation is certainly a better mechanism to handle design partitioning which is completely synthesizable. Therefore, it is recommended to use component instantiation rather than block statements.
10. A block can be nested within another block.
Explanation: Nesting of blocks is possible in VHDL. A block can be defined within another block. The nested block is called the child block and the other block is called parent block. Also, it is possible to define two signals with same name one in parent block and another in child block.
11. Which of the following is true about guarded blocks?
a) Guarded blocks can have only guarded statements
b) Guarded blocks can have both guarded as well as unguarded statements
c) Guarded blocks are executed when guarded expression is false
d) Guarded expression can have BIT type
Explanation: Guarded blocks can have both types of statements which are guarded and unguarded. Guarded assignment statements are those statements in which an assignment operator is followed by the keyword called GUARDED. For example, q <= GUARDED d AFTER 10 ns; here the assignment statement used is guarded statement.
12. Which of the following statement is used to describe regular structures?
d) GUARDED BLOCK
Explanation: Generate statement is used to describe regular structures such as array of blocks, component instances or processes. There are two types of generation schemes one is FOR generation and another is IF generation.
13. What will be the values of out1 and out2?
ARCHITECTURE bhv OF example IS CONSTANT out1 : BIT; CONSTANT out2 : BIT; BEGIN B1 : BLOCK CONSTANT S : BIT := 0; BEGIN B1-1 : BLOCK SIGNAL S : BIT := 1; BEGIN out1 <= S; END BLCOK B1-1; out2 <= S; END BLOCK B1; END bhv;
a) out1 = 0 and out2 = 0
b) out1 = 0 and out2 = 1
c) out1 = 1 and out2 = 0
d) out1 = 1 and out2 = 1
Explanation: Objects declared in a block are visible to that block and the blocks nested within. But, when a child block declares an object with same name as the one in parent block then child’s declaration overrides the parent’s object. Therefore, S used in block B1-1 will be 1 and another will be 0.
14. What is the use of FOR generation?
a) For describing the exceptional signals
b) For describing the repeating structures
c) For describing half adder circuit
d) For any exceptional cases of structure
Explanation: FOR generation is similar to for loop in traditional programming languages. Therefore, it can be used to describe structures which use some repeating pattern or similar patterns. It is not useful to design half adder by using FOR generation statement.
15. Which of the following is the use of IF generation?
a) To handle repeating pattern of design
b) To handle exceptional cases of design
c) To design full adder circuit
d) To connect input instances with output
Explanation: IF is a conditional generation scheme. It can be used to handle some conditional or exceptional cases of the structure. These exceptions may occur at the boundaries. So, IF generation is generally used at boundaries.
Sanfoundry Global Education & Learning Series – VHDL.
To practice all areas of VHDL, here is complete set of 1000+ Multiple Choice Questions and Answers.