This set of VHDL Interview Questions and Answers for Experienced people focuses on “Structural Modeling – 3”.
1. Which of the following is the correct order for a structural model in VHDL?
a) Libraries, Entity declaration, Component declaration, Component instantiation
b) Libraries, Component declaration, Entity declaration, Component instantiation
c) Libraries, Entity declaration, Component instantiation, Component declaration
d) Component declaration, Libraries, Entity declaration, Component instantiation
View Answer
Explanation: In a VHDL code, first of all, the packages and libraries are declared which are then followed by entity declaration. After the entity is declared, to model a circuit on the structural level, first all the components are declared after which they can be instantiated.
2. Refer to the model given below, which circuit is designed?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY design IS PORT(a, b, c : in BIT; x, y : out BIT); END design; ARCHITECTURE arch1 OF design IS COMPONENT xor2 IS PORT (i1, i2 : IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; COMPONENT and2 IS PORT(a1, a2 : IN STD_LOGIC; P : OUT STD_LOGIC); END COMPONENT; COMPONENT or2 IS PORT(d1, d2 : IN STD_LOGIC; r : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC; BEGIN X1: xor2 PORT MAP(a, b, s1); X2 : xor2 PORT MAP(s1, c, x); X3: and2 PORT MAP(a, b, s2); X4 : and2 PORT MAP(a, c, s3); X5: and2 PORT MAP(b, c, s4); X6: or2 PORT MAP(s2, s3, s5); X7: or2 PORT MAP(s4, s5, y); END arch1;
a) Half adder
b) Comparator 2- bits
c) Full adder
d) Can’t be determined
View Answer
Explanation: Though it is not possible to determine the circuits through its structural model until its components are not specified. In the above case, the components are clearly 2 input AND, OR and EXOR gates. These gates are connected to give one output called x as the EXOR of three inputs a, b and c. Another output y = ab + bc+ ac. So, it is a full adder circuit designed.
3. There is a special function called interconnect () to define interconnections between pins.
a) True
b) False
View Answer
Explanation: There is no special function for defining interconnection between two or more inputs or outputs. These interconnections are defined by using port map only. When we use same port for two or more components then they are interconnected.
4. Refer to the architecture given below, there are two outputs called x and y. The structure defined is a full adder circuit. Which of the outputs corresponds to sum output of the adder?
ARCHITECTURE arch1 OF design IS COMPONENT xor2 IS PORT (i1, i2 : IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; COMPONENT and2 IS PORT(a1, a2 : IN STD_LOGIC; P : OUT STD_LOGIC); END COMPONENT; COMPONENT or2 IS PORT(d1, d2 : IN STD_LOGIC; r : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC; BEGIN X1: xor2 PORT MAP(a, b, s1); X2 : xor2 PORT MAP(s1, c, y); X3: and2 PORT MAP(a, b, s2); X4 : and2 PORT MAP(a, c, s3); X5: and2 PORT MAP(b, c, s4); X6: or2 PORT MAP(s2, s3, s5); X7: or2 PORT MAP(s4, s5, x); END arch1;
a) y
b) x
c) s5
d) c
View Answer
Explanation: Since there are three components which are two inputs EXOR gate, AND gate and OR gate. The signal s1 is the output of EXOR of a and b inputs. This signal is further used to EXOR with c and the output is y. So, y = a EXOR b EXOR c, which corresponds to the sum output of the full adder.
5. Which modeling style is used in code given below?
ENTITY design IS PORT(a, b, c : in BIT; x, y : out BIT); END design; Architecture arch OF design IS BEGIN x <= a XOR b XOR c; y <= (a AND b) OR (b AND c) OR (a AND c); END arch; ARCHITECTURE arch1 OF design IS COMPONENT comp1 IS PORT (i1, i2 : IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; COMPONENT comp2 IS PORT(a1, a2 : IN STD_LOGIC; P : OUT STD_LOGIC); END COMPONENT; COMPONENT comp3 IS PORT(d1, d2 : IN STD_LOGIC; r : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC; BEGIN X1: comp1 PORT MAP(a, b, s1); X2 : comp1 PORT MAP(s1, c, x); X3: comp2 PORT MAP(a, b, s2); X4 : comp2 PORT MAP(a, c, s3); X5: comp2 PORT MAP(b, c, s4); X6: comp3 PORT MAP(s2, s3, s5); X7: comp3 PORT MAP(s4, s5, y); END arch1;
a) Behavioral and structural
b) Structural
c) Dataflow
d) Dataflow and Structural
View Answer
Explanation: Since there are two architectures defined for the entity ‘design’. So, two modeling styles are used. In the first architecture, the data flow from inputs to outputs is described by using Boolean equations therefore, it is dataflow modeling. In the second architecture, components are declared and instantiated. So, it is structural model.
6. What is the correct syntax for mapping a GENERIC parameter in structural modeling?
a) label : component_name GENERIC MAP(parameter_list) PORT MAP(port_list)
b) label : component_name GENERIC MAP(parameter_list)
c) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
d) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
View Answer
Explanation: Generic is a constant parameter which can be used in structural modeling. But, generic is not a component as such. It can be used as a specification to any component. The correct syntax to use a generic is GENERIC MAP followed by a PORT MAP function.
7. It is possible to use a GENERIC parameter as a separate component.
a) True
b) False
View Answer
Explanation: A Generic is just a constant and hence can’t have any input or output ports. It is only used with any component to describe its specification. For example, any component needs an array of input ports, the index value of that array can be defined by using generic parameter and that generic parameter can be used with PORT MAP to map the ports.
8. A component instantiation statement generates a(n) _______ of the component.
a) Class
b) Behavior
c) Structure
d) Object
View Answer
Explanation: By ending the component declaration, its object is created which can be used further in the code to use the declared component. The component instantiation statement uses this object and inherits the properties of component declared. These properties include all the ports and their number.
9. The structural code for 4-bit adder is given below.
COMPONENT adder IS GENERIC (n : INTEGER := 3); PORT(input : IN BIT_VECTOR(n DOWNTO 0); output : OUT BIT_VECTOR(n DOWNTO 0)); END COMPONENT;
If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a) n
b) input
c) output
d) component
View Answer
Explanation: The only way to change it is by changing the value of n. If n is changed from 3 to 7, then it will have 8 input bits and 8 output bits. In this way, by using generic, the whole structure can be altered easily. Also, it may be noted if the value of the generic is not specified, then it will take the value used at the time of entity declaration.
10. What is the other name for implicit mapping?
a) Nominal mapping
b) Positional mapping
c) Explicit mapping
d) Inclusive mapping
View Answer
Explanation: Implicit mapping is another name for positional mapping in which only ports are specified without using any assignments. Similarly, nominal mapping is the other name for explicit mapping which uses proper assignments to instantiate the component. In VHDL, there are only two types of mapping called Positional and nominal, there is no mapping called inclusive mapping.
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