This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Signal Assignment – 1”.
1. The signal assignment is considered as a ________
a) Concurrent statement
b) Sequential statement
c) Subprogram
d) Package declaration statement
View Answer
Explanation: The signal assignment statement is typically considered a concurrent statement rather than a sequential statement. However, the statement can be used as a sequential statement as well but has a side effect of obeying the general rules for when the left operand is actually updated.
2. How can we use an assignment statement as a sequential assignment?
a) By using keyword WAIT
b) By using a delay mechanism
c) By using conditional statements
d) By using it in any process
View Answer
Explanation: The assignment statements can appear either in architecture or in a process. According to this only, the signal assignment is classified as a concurrent and sequential assignment. If the signal assignment is done in a process, then it is a sequential assignment, otherwise it is a concurrent assignment.
3. The sequential assignment statement is activated, whenever ________
a) The waveform associated changes its value
b) The process is terminated
c) The execution is scheduled
d) The value of the target is needed
View Answer
Explanation: The sequential assignment statement appears inside a process. The statements inside the process are sequential statements and the assignment is activated when the process ends. So, the assignment will take place at the time of process termination only.
4. The concurrent assignment statement is activated whenever ______
a) The execution is scheduled
b) The value of the target is needed
c) The waveform associated changes its value
d) The process is terminated
View Answer
Explanation: Concurrent assignment statement has nothing to do with processes. It is executed whenever the waveform associated with it changes its value. The value of the target is updated every time the value of waveform changes.
5. Which of the following is correct syntax for a signal assignment statement (if {} specifies an optional part)?
a) target <= {delay_mechanism} waveform;
b) target <= delay_mechanism waveform;
c) target <= delay_mechanism {waveform};
d) target <= {delay_mechanism} {waveform} value;
View Answer
Explanation: The proper signal assignment is shown in option target <= {delay_mechanism} waveform;. The ‘target’ gets the value of ‘waveform’ by executing the delay mechanism. The delay mechanism is ,however, optional but is used most of the times for better timing performance of the circuit.
6. The conditional assignment statement is a _________ assignment.
a) Sequential
b) Concurrent
c) Selected
d) None of the above
View Answer
Explanation: The conditional statement is a type of concurrent assignment statement in which the assignment is executed only if the condition specified is true. It may be noted that the condition is Boolean i.e. it may have only two values true or false.
7. Sequential assignments are synthesizable.
a) True
b) False
View Answer
Explanation: Generally, sequential assignments are synthesizable by EDA tools. The assignment statement must be using some operators and types. The only case when these assignments are not synthesizable is when the types and operators are acceptable to the synthesis tools.
8. Delays are generally ignored in ________ assignments statements.
a) Concurrent
b) Conditional
c) Sequential
d) Selected
View Answer
Explanation: Conditional and selected assignments are type of concurrent assignment. In case of concurrent assignments delays are usually taken into consideration. Whereas, there is no use of delays in sequential assignments since it is executed at the end of process. So, there is no need for delay in sequential assignments.
9. Which of the following can’t be a mode for target operand of assignment statement?
a) BUFFER
b) INOUT
c) OUT
d) IN
View Answer
Explanation: The left operand of assignment statement, called the target operand is always assigned the value of another operand. There is no chance of using IN type target on the left side of an assignment statement. It is mandatory that the direction of target include output.
10. Which of the following is a variable assignment statement?
a) <=
b) :=
c) =>
d) ==
View Answer
Explanation: To assign a value to variable, a variable assignment statement is used. The symbol used for variable assignment is ‘:=’ whereas when we assign some value to a signal, <= statement is used. In case of variables if we use <= instead of :=, there can be some problem with the delay mechanisms.
11. Which of the following is a keyword used for conditional assignment?
a) IF
b) WHEN
c) FOR
d) END
View Answer
Explanation: Conditional statement is an assignment statement in which a condition is first tested and then assignment occurs. It uses the keyword WHEN to assign value to a signal conditionally. For example, y <= ‘1’ WHEN x = ‘0’. This is a conditional statement that will assign value 1 to signal y only when signal x is low.
12. For a signal used in sequential assignment, it can have _______ driver(s).
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: Sequential assignment statement is the one that is used in a process. This statement is executed at the end of the process. No matter how many signal assignment statements are used, only the last one is taken into consideration(for 1 signal). So, in a process, one signal can have only 1 driver.
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