VHDL Questions and Answers – EDA Tools

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “EDA Tools”.

1. What is the full form of VHDL?
a) Verilog Hardware Description Language
b) Very High speed Description Language
c) Variable Hardware Description Language
d) Very high speed Hardware Description Language
View Answer

Answer: d
Explanation: Most people confuse Verilog Hardware Description Language with VHDL but, VHDL means VHSIC Hardware Description Language where VHSIC is the acronym for Very High Speed Integrated Circuits.

2. What is the basic use of EDA tools?
a) Communication of Electronic devices
b) Fabrication of Electronics hardware
c) Electronic circuits simulation and synthesis
d) Industrial automation
View Answer

Answer: c
Explanation: EDA expands to Electronic Design Automation and these tools are used for synthesis, implementation and simulation of Electronic circuits on the software itself.

3. After compiling VHDL code with any EDA tool, we get __________
a) Final device
c) Optimized netlist
d) Netlist
View Answer

Answer: d
Explanation: After entering the code into any EDA tool, we need to compile the code. When the compilation is complete, then we get the complete netlist of the system designed by using VHDL. After which optimization process is used to optimize the netlist and then by placement and routing we get final Physical device.

4. Which of the following is not an EDA tool?
a) Visual C++
b) Quartus II
c) Xilinx ISE
d) MaxPlus II
View Answer

Answer: a
Explanation: Quartus II EDA tool is used for Altera CPLD and FPGA devices. Similarly, Xilinx ISE is used for Xilinx CPLD/FPGA devices. MaxPlus is also an advanced EDA tool for Altera CPLDs. Visual C++ is the compiler for C and C++ languages.

5. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________
a) Simulation
b) Synthesis
c) Optimization
d) Verification
View Answer

Answer: b
Explanation: Synthesis means to generate netlist, i.e. describing the circuit by the relation between inputs and outputs by using logic equations. Simulation is whereas to check the correctness of VHDL code and Optimization is to optimize the netlist; optimization is performed after the synthesis. Verification similarly uses different EDA tool to perform gate level verification.

6. Place and Route EDA tools are used to take the design netlist and implement the design in the device.
a) True
b) False
View Answer

Answer: a
Explanation: Place and Route tools are used to take the netlist and implement it on the target device by taking various factors into consideration like Timing constraints and some device information.

7. An Antifuse programming technology is associated with _________
a) CPLDs
b) FPGAs
c) SPLDs
d) ASICs
View Answer

Answer: b
Explanation: Antifuse technology is used to burn the information, from place and route tools, into appropriate fuses in the FPGAs.

8. Which of the following is not a back end EDA tool?
a) Floor planning tools
b) Placement tools
c) Routing tools
d) Simulators
View Answer

Answer: d
Explanation: Simulators are the tools which are used at the front end and all other tools are used at the back end.

9. What are the differences between simulation tools and synthesis tool?
a) Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits
b) Simulators and Synthesis tools works exactly same
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation
d) Simulation finds the error in the code and Synthesis tool corrects the code
View Answer

Answer: c
Explanation: Simulators test basic logic and working of the circuit described in the code and Synthesis allows to take timing factor and other factors into consideration while simulation.

10. What is the extension of the netlist file; input to the place and route EDA tools?
b) SDF
c) TXT
d) CPP
View Answer

Answer: a
Explanation: EDIF and XNF are the netlist files; whereas SDF is the file of timing information.TXT is the extension of a simple text file and CPP is the C++ source file.

Sanfoundry Global Education & Learning Series – VHDL.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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