# VHDL Questions and Answers – Implementing Gates with Different Modelling – 1

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Gates with Different Modelling – 1”.

1. Which of the following is a basic building block of a digital logic?
a) Wires
b) Nets
c) Gates
d) Flip-flops

Explanation: Any kind of digital logic can be synthesized by basic logic gates like or gate, and gate, not gate etc. By using these simple gates, we may synthesize many difficult circuits or functions. So, gates are the building block for any digital logic.

2. Which of the following gate is a universal gate?
a) AND
b) NAND
c) EXOR
d) EXNOR

Explanation: NAND and NOR are two universal gates. They are called so because we may implement any kind of basic logic gate by using any of these two universal logic gates. By using NAND or NOR, we may implement AND, OR, NOT and EXOR gates.

3. By how many modeling styles, the gates in VHDL can be implemented?
a) 1
b) 2
c) 3
d) 4

Explanation: There are three modeling styles in VHDL in which we may implement any kind of logic or logic gate. These modeling styles are behavioral modeling, dataflow modeling and structural modeling.

4. Which of the following is not needed when modeling a simple gate?
a) Library
b) Entity
c) Architecture
d) Configuration

Explanation: Modeling a gate is a really easy task. There is no need for adding some CONFIGURATIONS to the design. The gates can be designed with any modeling style without using any kind of configuration statement. Also, describing architecture is essential along with entity. Package is needed to have some basic functions.

5. Which kind of modeling is used in the following description?

```ARCHITECTURE my_arch OF my_design IS
BEGIN
c<= a OR b;
END my_arch;```

a) Behavioral
b) Data flow
c) Structural
d) Behavioral and Dataflow

Explanation: In such cases, where the direct relation between inputs and outputs are described. A flow of data from the input side to the output side is described by using logic functions. Therefore, it is the case of dataflow modeling.

6. What is the type of modeling used in the code given below?

```ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
‘0’ WHEN OTHERS;
END my_arch;```

a) Behavioral
b) Dataflow
c) Structural
d) Combinational

Explanation: When the architecture describes the behavior of the circuit with respect to different combinations of inputs, then it is called behavioral modeling. The behavioral modeling uses selected assignment to show the value of output for different inputs.

7. The architecture describes _______ gate implemented by _________ modeling.

```ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= NOT(a OR b);
END my_arch;```

a) Or, behavioral
b) Not, Dataflow
c) Nor, behavioral
d) Nor, Dataflow

Explanation: Since, the logic function is used to show the flow of data from input to the output. Therefore, The architecture describes the dataflow model of a gate. Also, the function is a not function performed on the output of or function. Therefore, the design is for NOR gate.

8. Which logic gate is described by the following model, also specify the type of modeling used?

```ARCHITECTURE my_arch OF my_design IS
BEGIN
WITH ab SELECT
y <= 0 WHEN “11”
1 WHEN OTHERS
END my_arch;```

a) NAND, Behavioral
b) NOR, Behavioral
c) NAND, Dataflow
d) NOR, Dataflow

Explanation: It is clear from the architecture that the description represents a behavioral model. Now, the gate described must be the one which has low output when all of its inputs are low. Otherwise, the output is high. This is the case with NAND gate. So, the given logic is behavioral model of NAND gate.

9. Which of the logic gate is described by the following model?

```ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT my_comp IS
PORT( a, b : IN std_logic;
y     : OUT std_logic);
END COMPONENT;
L1 : my_comp PORTMAP( x, y, z);
END my_arch;```

a) OR
b) NOT
c) AND
d) Can’t be determined

Explanation: The description is the structural model for any gate. But, it is not possible to determine which kind of gate it is. The given information is not sufficient to determine the type of the gain. It can be concluded that structural model alone is not adequate to describe any component completely.

10. The design below can’t be of ________gate.

```ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT or_comp IS
PORT( a, b : IN std_logic;
y     : OUT std_logic);
END COMPONENT;
L1 : or_comp PORTMAP( x, y, z);
END my_arch;```

a) AND
b) OR
c) NOT
d) NAND 