VHDL Questions and Answers – Signal Assignment – 2

This set of VHDL test focuses on “Signal Assignment – 2”.

1. The selected concurrent statement is equivalent to ________ sequential statement.
a) If else
b) Loop
c) Wait
d) Case
View Answer

Answer: d
Explanation: Selected concurrent assignment statement is used when the target signal has to choose one value out of n(say) values. This is similar to the case statement used in the process. It uses the keyword ‘SELECT’ to select one value.

2. Those statement which are placed under ________ are concurrent.
a) Process
b) Function
c) Architecture
d) Procedure
View Answer

Answer: c
Explanation: VHDL code, in general, is a concurrent code. Only statements placed under Process, Function or Procedure are executed sequentially. All other statements are concurrent statements.

3. In case of concurrent assignment, order of statements doesn’t matter.
a) True
b) False
View Answer

Answer: a
Explanation: Since execution of a concurrent statement is parallel and an assignment statement has to be executed whenever the signal associated with it changes its value. Therefore, there is no restriction on the order of the statements.

4. Which of the following can’t be implemented with concurrent statements only?
a) Multiplexer
b) Decoder
c) Adder
d) Counter
View Answer

Answer: d
Explanation: In general, we use concurrent code to build combinational circuits and the reason is that order of statements is not a problem. So, we can’t use purely concurrent code to obtain sequential logic circuits due to use of clock and processes. Hence, counter can’t be designed by using concurrent code only.

5. Variable assignment statement executes in ______ time.
a) Immediately(zero)
b) After delay specified
c) After one clock cycle
d) After two clock cycles
View Answer

Answer: a
Explanation: When a variable is assigned a value, the assignment executes in zero simulation time. In other words, it changes the value of variable immediately. Also, the delay mechanism is used in the signal assignment but not in variable assignment. Variable assignment doesn’t use any delay mechanism.

6. In the signal assignment statement, which delay is used?

x <= 1 AFTER 10ns

a) Transport delay
b) Inertial delay
c) Delta delay
d) Wire delay
View Answer

Answer: b
Explanation: Inertial delay is the default delay in VHDL in which only last value is persisted ignoring all other delays. In the case of inertial delay, there is no need of specifying anything like we need to write TRANSPORT to specify the transport delay.

7. Inertial delay in Signal assignment is useful to ___________
a) Specify wire delay
b) Accumulate delay
c) Ignore input glitches
d) No use
View Answer

Answer: c
Explanation: Inertial delay assignment takes only last assignment statement into consideration ignoring all the preceding assignments. So, any intermediate change will be ignored. Therefore, It is useful in ignoring input glitches.

8. Which of the following statement is a zero delay statement?
a) y <= x AFTER 10 ns
b) y <= TRANSPORT x AFTER 10 ns
c) y <= x
d) y := x AFTER 10 ns
View Answer

Answer: d
Explanation: Signal assignment always have some amount of delay either inertial or transport. If there is no delay specified in signal assignment, even then the delta delay is used to assign value. Only variable assignment is executed immediately also the delay is ignored. Therefore, option d is zero delay statement.

9. Which of the following statement can’t be used to assign values in behavioral modeling of OR Gate?
a) Simple concurrent assignment
b) Sequential assignment
c) Conditional concurrent assignment
d) Selected concurrent assignment
View Answer

Answer: d
Explanation: In the behavioral modeling, various output values are described w.r.t different combination of input values. A conditional concurrent assignment and selected concurrent assignment can add some condition for assigning values. Same can be done with sequential statements. By using simple concurrent statements, it is not possible to realize or gate.

10. Which of the following is not an assignment statement?
a) <=
b) :=
c) =>
d) :>
View Answer

Answer: d
Explanation: There are three assignment statements in VHDL. <= is a signal assignment statement, := is used for variable assignment and => is used at the time of mapping the components and is used with ‘OTHERS’. These are 3 type of assignment operators.

11. OTHERS keyword is used with which kind of assignment?
a) Concurrent
b) Sequential
c) Selected
d) Conditional
View Answer

Answer: c
Explanation: Selected concurrent assignment statement is used when you have to choose one value out of n values. In that case WHEN and OTHERS keywords are used. OTHERS is similar to the ELSE statement which will be selected when all the conditions are false.

12. The following code represents which of the logic gates?

y <= 1 WHEN11;0	WHEN OTHERS;

a) And gate
b) Or gate
c) Not gate
d) Nand gate
View Answer

Answer: a
Explanation: Here, the selected signal assignment is used in which the output is getting the value 1 when both the inputs are 1. Otherwise, the output is 0. This is clearly the case of 2 inputs AND gate.

Sanfoundry Global Education & Learning Series – VHDL.

To practice all areas of VHDL for tests, here is complete set of 1000+ Multiple Choice Questions and Answers.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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