VHDL Questions and Answers – Data Conversion
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Data Conversion”. 1. Refer to the VHDL code given below, which of the following line has error? Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line … Read more