Microprocessors Questions and Answers – Interrupt and Stack of 8051 -1

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Interrupt and Stack of 8051 -1”.

1. Which of the following is an external interrupt?
a) INT0(active low)
b) INT2(active low)
c) Timer0 interrupt
d) Timer1 interrupt
View Answer

Answer: a
Explanation: INT0(active low) and INT1(active low) are two external interrupt inputs provided by 8051.

2. The interrupts, INT0(active low) and INT1(active low) are processed internally by flags
a) IE0 and IE1
b) IE0 and IF1
c) IF0 and IE1
d) IF0 and IF1
View Answer

Answer: a
Explanation: The interrupts, INT0(active low) and INT1(active low) are processed internally by the flags IE0 and IE1.

3. The flags IE0 and IE1, are automatically cleared after the control is transferred to respective vector if the interrupt is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
View Answer

Answer: b
Explanation: If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are automatically cleared after the control is transferred to respective vector.
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4. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
View Answer

Answer: a
Explanation: If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are controlled by external interrupt sources themselves.

5. The pulses at T0 or T1 pin are counted in
a) timer mode
b) counter mode
c) idle mode
d) power down mode
View Answer

Answer: b
Explanation: In counter mode, the pulses are counted at T0 or T1 pin.
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6. In timer mode, the oscillator clock is divided by a prescalar
a) (1/8)
b) (1/4)
c) (1/16)
d) (1/32)
View Answer

Answer: d
Explanation: In timer mode, the oscillator clock is divided by a prescalar (1/32) and then given to the timer.

7. The serial port interrupt is generated if
a) RI is set
b) RI and TI are set
c) Either RI or TI is set
d) RI and TI are reset
View Answer

Answer: c
Explanation: The serial port interrupt is generated if atleast one of the two bits, RI and TI is set.
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8. In serial port interrupt, after the control is transferred to the interrupt service routine, the flag that is cleared is
a) RI
b) TI
c) RI and TI
d) None
View Answer

Answer: d
Explanation: In serial port interrupt, after the control is transferred to the interrupt service routine, neither of the flags are cleared.

9. The atleast number of machine cycles for which the external interrupts that are programmed level-sensitive should remain high is
a) 1
b) 2
c) 3
d) 0
View Answer

Answer: b
Explanation: The external interrupts, programmed level-sensitive should remain high for atleast 2 machine cycles.
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10. If the external interrupts are programmed edge sensitive, then they should remain high for atleast
a) 0 machine cycle
b) 2 machine cycles
c) 1 machine cycle
d) 3 machine cycles
View Answer

Answer: c
Explanation: If the external interrupts are programmed edge sensitive, then they should remain high for atleast one machine cycle and low for atleast one machine cycle, for being sensed.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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