# Microprocessors Questions and Answers – Timings and Delays

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Timings and Delays”.

1. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T

Explanation: The duration of execution of the loop is the product of number of clock cycles and the period of the clock cycle at which microprocessor is running.

2. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration

Explanation: As the microprocessor executes each instruction corresponding loop counter value decreases and the microprocessor executes the instructions till the loop counter becomes zero.

3. In case of subroutines, the actual number of instructions executed by the processor depends on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none

Explanation: In case of subroutines or interrupt service routines, the number of instructions executed by the processor depends on the length of procedure (or subroutine) or length of interrupt service routine along with the main calling program.

4. The step included in generating delays is
a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned

Explanation: The delays can be generated step wise.

5. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency

Explanation: The count N can be defined as the required time delay by the duration for execution of the loop once.
Count, N = required delay (Td)/duration for execution of the loop once (n*T).
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6. In the instruction set,

```      MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET```

if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles

Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.

7. In the instruction set,

```      MOV CX, BA03H
WAIT: DEC CX
NOP
JNZ WAIT
RET```

if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles

Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.

8. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay

Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the limitation on the maximum delay that can be generated using the instructions.

9. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used

Explanation: One or more count registers can be used to serve large delays.

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