This set of Microprocessors Quiz focuses on “Instruction Set Features -2”.
1. In ‘Rotate source, count’ instructions, if the CF is equal to MSB of operand (source) then
a) TF is cleared
b) OF is cleared
c) TF is set
d) OF is set
View Answer
Explanation: If CF is equal to MSB of operand (source), the overflow flag is cleared, otherwise, it is set to 1.
2. The instruction that affects the flags is
a) IMUL
b) INSW
c) INSB
d) POP*A
View Answer
Explanation: No flags are affected by the instructions, INSW, INSB and POP*A.
3. A general protection exception is generated, if the value of
a) CPL is equal to that of IOPL
b) CPL is less than that of IOPL
c) CPL is greater than that of IOPL
d) None of the mentioned
View Answer
Explanation: When the value of CPL is greater than that of IOPL, a general protection exception is generated.
4. While executing the instruction, OUTSW, the SI is incremented by
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: The SI is automatically incremented by 1 for byte (OUTSB) and 2 for word (OUTSW) operations.
5. The instruction that is used to exit the procedure is
a) QUIT
b) STOP
c) LEAVE
d) EXIT
View Answer
Explanation: The instruction, LEAVE, is generally used with high level languages, to exit a procedure.
6. The instruction that determines the number of bytes, to be copied into the new stack frame, from the previous stack is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
View Answer
Explanation: The ENTER instruction prepares a stack structure for parameters of a procedure to be executed further. This instruction determines the number of bytes to be copied, into the new stack frame, from the previous stack.
7. The instruction that is used to check whether a signed array offset is within the limit, defined for it by the starting and ending index is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE
View Answer
Explanation: The BOUND instruction is used to check whether a signed array offset is within the limit defined for it, by the starting and ending index.
8. The CLTS (Clear Task Switch Flag) instruction records every execution of WAIT and ESC and is trapped if the flag(s)
a) PE (Protection Enable) and TS (task switch) flags are set
b) Emulate Processor extension flag is set
c) MP flag and task switched flag is set
d) PE and MP flag is set
View Answer
Explanation: The CLTS (Clear Task Switch Flag) instruction records every execution of WAIT and ESC, and is trapped, if the MP flag and task switched flag is set.
9. The instruction that determines whether the segment pointed to, by a 16-bit register, can be accessed from the current privilege level is
a) RPL
b) CPL
c) ARPL
d) VERR
View Answer
Explanation: The VERR/VERW instructions determine whether the segment pointed to, by a 16-bit register, can be accessed from the current privilege level.
10. The instruction that loads 6 bytes from a memory block, pointed to by the effective address of the operand, into global descriptor table register is
a) LLDT
b) SGDT
c) LGDT
d) None of the mentioned
View Answer
Explanation: The LGDT (load global descriptor table register) loads 6 bytes from a memory block, pointed to by the effective address of the operand, into global descriptor table register.
11. In LGDT instruction, while loading 6 bytes, the first word is loaded into the field of
a) LIMIT field
b) BASE field
c) Either LIMIT or BASE field
d) None of the mentioned
View Answer
Explanation: While loading the 6 bytes, the first word is loaded into the LIMIT field of the descriptor table register. The next three bytes are loaded into the BASE field of the register, and the remaining byte is ignored.
Sanfoundry Global Education & Learning Series – Microprocessors.
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