This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “80287 Math Coprocessor -1”.
1. Which of the following is not a block of an architecture of 80287?
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
View Answer
Explanation: The three blocks of an internal architecture of 80287 are:
1. bus control logic
2. data interface and control unit
3. floating point unit.
2. The unit that provides and controls the interface, between the internal 80287 bus and 80286 bus via data buffer is
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
View Answer
Explanation: The bus control logic provides and controls the interface, between the internal 80287 bus and 80286 bus via data buffer.
3. The data interface and control unit consists of
a) status and control words
b) tag words and error pointers
c) instruction decoders
d) all of the mentioned
View Answer
Explanation: The data interface and control unit contains status and controls words, TAG words and error pointers.
4. The word that optimizes the NDP performance, by maintaining a record of empty and non-empty register locations is
a) Status and control words
b) TAG words
c) Error pointers
d) All of the mentioned
View Answer
Explanation: The TAG word optimizes the NDP performance by maintaining a record of empty and non-empty register locations. It helps the exception handler to identify special values in the contents of the stack locations.
5. The part of the data interface and control unit, that points to the source of exception generated is
a) Status and control words
b) TAG words
c) Error pointers
d) None of the mentioned
View Answer
Explanation: The error pointers point to the source of exception (address of the instruction that generated the exception) generated.
6. The data bus in a floating point unit is of
a) 16 bits
b) 32 bits
c) 64 bits
d) 84 bits
View Answer
Explanation: The data bus in a floating point unit is of 84-bits. Out of this 84-bits, the lower 68 bits are significant (mantissa) data bit, the next 16 bits are used for the exponent.
7. The arrangement of data that is to be shifted successively, whenever required for the execution, is done by
a) error pointer
b) data buffer
c) barrel shifter
d) none of the mentioned
View Answer
Explanation: The barrel shifter arranges and presents the data to be shifted successively, whenever required for the execution.
8. The word that is used to select one of the processing options, among the provided ones is
a) status word
b) control word
c) status and control words
d) none of the mentioned
View Answer
Explanation: The control word is used to select one of the processing options, among the ones provided by 80287.
9. After reset of 80287, the control bit that is initialized to zero is
a) masking bits
b) precision control bits
c) rounding control bits
d) infinity control bits
View Answer
Explanation: The infinity control bit is initialized to zero after reset.
10. The bits that are modified depending upon the result of the execution of arithmetic instructions are
a) masking bits
b) rounding control bits
c) condition code bits
d) error summary bits
View Answer
Explanation: The condition code bits are similar to the flags of a CPU. These are modified depending upon the result of the execution of arithmetic instructions.
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