This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Interrupt Structure of 8051”.
1. The external interrupts of 8051 can be enabled by
a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned
View Answer
Explanation: The external interrupts namely INT0(active low) and INT1(active low) can be enabled and programmed using the least significant four bits of TCON register and the Interrupt enable and priority registers.
2. The bits that control the external interrupts are
a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2
View Answer
Explanation: The bits, EX0 and EX1 individually control the external interrupts, INT0(active low) and INT1(active low). If INT0(active low) and INT1(active low) interrupts are to be enabled then the bits EX0 and EX1 must be set respectively.
3. EA bit is used to
a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned
View Answer
Explanation: Using EA bit, all the interrupts can be enabled or disabled. Using the individual respective bit, the respective interrupt can be enabled or disabled.
4. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: Each interrupts level of 8051 can have two levels of priority namely level 0 and level 1. Level 1 is considered as a higher priority level compared to level 0.
5. The priority level of an interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none
View Answer
Explanation: SI interrupt is programmed for level 1 priority.
6. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) All of the mentioned
View Answer
Explanation: The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.
7. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none
View Answer
Explanation: All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in the same cycle.
8. The minimum duration of the active low interrupt pulse for being sensed without being lost must be
a) greater than one machine cycle
b) equal to one machine cycle
c) greater than 2 machine cycles
d) equal to 2 machine cycles
View Answer
Explanation: The minimum duration of the active low interrupt pulse should be equal to the duration of one machine cycle for being sensed, else it will be lost.
9. If two interrupts, of higher priority and lower priority occur simultaneously, then the service provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) lower & higher priority interrupts
d) none of the mentioned
View Answer
Explanation: If two interrupts, occur simultaneously, then the one with higher priority level and early polling sequence will receive service. The other one with lower priority may get lost there, as there is no mechanism for storing the interrupt requests.
10. For an interrupt to be guaranteed served it should have duration of
a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles
View Answer
Explanation: For an interrupt to be guaranteed served it should have duration of two machine cycles.
11. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) Instruction that writes to IE register
c) Instruction that writes to IP register
d) All of the mentioned
View Answer
Explanation: The service to an interrupt will be delayed if it appears during the execution of RETI instruction or the instruction that writes to IE/IP registers.
Sanfoundry Global Education & Learning Series – Microprocessors.
Here’s the list of Best Books in Microprocessors.
- Check Computer Science Books
- Practice Electronics & Communication Engineering MCQs
- Check Microprocessor Books
- Check Electronics & Communication Engineering Books
- Practice Computer Science MCQs
