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Microprocessors Multiple Choice Questions | MCQs | Quiz

Microprocessor Interview Questions and Answers
Pratice Microprocessor questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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•   Machine Language Formats
•   8086 Addressing Modes
•   8086/8088 Instruction Set-1
•   8086/8088 Instruction Set-2
•   8086/8088 Instruction Set-3
•   Assembler Directives
•   Instructions Do's & Don'ts
•   Assembler Programming
•   Stack
•   8086/8088 Stack Structure
•   Interrupt Service Routines
•   8086/8088 Interrupt Cycle
•   Non Maskable Interrupt
•   Interrupt Programming
•   Macros
•   Timings & Delays
•   Semiconductor Interfacing
•   Dynamic RAM Interfacing
•   Interfacing I/O Ports
•   PIO 8255
•   8255 Operation Modes
•   Analog - Digital Converters
•   Stepper Motor Interfacing
•   8254 Interval Timer
•   8259A Interrupt Controller
•   8279 Keyboard Controller
•   8251 USART
•   8257 DMA Controller
•   DMA Transfer & Operations
•   8237 DMA Interface - 1
•   8237 DMA Interface - 2
•   High Storage Capacity
•   Interconnection Topologies
•   Software Aspects
•   Numeric Processor 8087 - 1
•   Numeric Processor 8087 - 2
•   8089 I/O Processor
•   Bus Arbitration & Control
•   Tightly Coupled Systems
•   Multi Microprocessor
•   80286 Salient Features
•   80286 Internal Architecture
•   80286 Signal Descriptions
•   Real Addressing Mode
•   PVAM - 1
•   PVAM - 2
•   Privilege
•   Protection
•   Special Operations
•   80286 System Configuration
•   Bus Hold & HLDA
•   Instruction Set Features - 1
•   Instruction Set Features - 2
•   80287 Math Coprocessor-1
•   80287 Math Coprocessor-2
•   80386DX Salient Features
•   ↓ 80386 ↓
•   Architecture & Signals
•   Register Organisation - 1
•   Register Organisation - 2
•   80386 Data Types
•   80386 Real Address Mode
•   Segmentation
•   Paging
•   80387 Coprocessor
•   80386 Instruction Set
•   80486DX Coprocessor
•   80586 (Pentium) Features
•   System Architecture
•   Intel MMX Architecture
•   MMX Data Types
•   MMX Instruction Set
•   Pentium-Pro & Pentium2 - 1
•   Pentium-Pro & Pentium2 - 2
•   Pentium 4 Features - 1
•   Pentium 4 Features - 2
•   Hyperthreading Technology
•   Pentium Hyperthreading
•   Formal Verification
•   Hybrid Architecture - 1
•   Hybrid Architecture - 2
•   8051 Architecture
•   8051 Register Set
•   8051 Interrupt & Stack - 1
•   8051 Interrupt & Stack - 2
•   8051 Addressing Modes
•   8051 Instruction Set - 1
•   8051 Instruction Set - 2
•   8051 Ports Interfacing - 1
•   8051 Ports Interfacing - 2
•   8051 Interrupt Structure
•   Serial Communication Unit
•   Power Control Register

Best Reference Books

Microprocessor Books
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Microprocessors Questions and Answers – Semiconductor Memory Interfacing

Posted on March 18, 2014 by Manish

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Semiconductor Memory Interfacing”.

1. The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
View Answer

Answer: b
Explanation: The semiconductor memories are organised as two dimension of array which consists of rows and columns.

2. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
View Answer

Answer: c
Explanation: The bits in a selected location are accessible using data bus.

3. To address a memory location out of N memory locations, the number of address lines required is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)
View Answer

Answer: a
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of memory, 12 address lines are required since log(4KB) =log(4*1024)=log(212)=12.

4. If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
a) 512
b) 1024
c) 2048
d) none
View Answer

Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.

5. In static memory, the upper 8-bit bank of available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
View Answer

Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.

6. In static memory, the lower 8-bit bank of available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
View Answer

Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.

7. In most of the cases, the method used for decoding that may be used to minimise the required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
View Answer

Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.

8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
View Answer

Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.

9. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
View Answer

Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.

10. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
View Answer

Answer: c
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected.

Sanfoundry Global Education & Learning Series – Microprocessors.

Here’s the list of Best Reference Books in Microprocessors.

To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice Questions and Answers.
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Microprocessors Questions and Answers – Dynamic RAM Interfacing »

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