Microprocessors Questions and Answers – Architecture and Signal Descriptions of 80386

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Architecture and Signal Descriptions of 80386”.

1. Which of the units is not a part of the internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
View Answer

Answer: d
Explanation: The internal architecture of 80386 is divided into three sections namely, central processing unit, memory management unit and bus interface unit.

2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
View Answer

Answer: c
Explanation: The central processing unit is further divided into the execution unit and instruction unit.

3. The unit that is used for handling data, and calculates offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
View Answer

Answer: b
Explanation: The execution unit has eight general purpose and eight special purpose registers, which are either used for handling the data or calculating the offset addresses.
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4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer

Answer: c
Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code queue, after decoding them so as to pass it to the control section, for deriving the necessary control signals.

5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
View Answer

Answer: d
Explanation: The barrel shifter speeds up all shift and rotate operations.
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6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
View Answer

Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.

7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
View Answer

Answer: d
Explanation: The segmentation unit allows the use of two address components. They are: segment and offset for relocation and sharing of code and data.
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8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
View Answer

Answer: c
Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.

9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
View Answer

Answer: b
Explanation: The paging unit works under the control of the segmentation unit; i.e. each segment is further divided into pages.
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10. The unit that provides a four level protection mechanism, for system’s code and data against application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
View Answer

Answer: b
Explanation: The segmentation unit provides a four level protection mechanism, for protecting and isolating the system’s code and data, from those of the application program.

11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer

Answer: c
Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.

12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit
View Answer

Answer: b
Explanation: The data buffer interfaces the internal data bus with the system bus.

13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver
View Answer

Answer: c
Explanation: The address driver drives the bus enable and address signals A0-A31.

14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned
View Answer

Answer: b
Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus cycles.

15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
View Answer

Answer: c
Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of slow devices with the CPU.

16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ
View Answer

Answer: d
Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data word for the coprocessor.

17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned
View Answer

Answer: c
Explanation: The pipeline and dynamic bus sizing units handle the related control signals.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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