This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Dynamic RAM Interfacing”.
1. The advantage of dynamic RAM is
a) high packing density
b) low cost
c) less power consumption
d) all of the mentioned
Explanation: The dynamic RAM is advantageous than the static RAM as it has a higher packing density, lower cost and less power consumption.
2. Whenever a large memory is required in a microcomputer system, the memory subsystem is generally designed using
a) Static RAM
b) Dynamic RAM
c) Both static and dynamic RAM
Explanation: Dynamic RAM is preferred for large memory.
3. If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires
a) 1 transistor along with capacitance
b) 2 transistors along with resistance
c) 3 transistors along with diode
d) 2 transistors along with capacitance
Explanation: The hardware complexity of dynamic RAM is lesser than that of static RAM.
4. To store the charge as a representation of data, the basic dynamic RAM cell uses
Explanation: The basic dynamic RAM cell uses capacitance to store the charge as a representation of data. This capacitor is manufactured as a diode that is reverse biased so that the storage capacitance is obtained.
5. The process of refreshing the data in the RAM to reduce the possibility of data loss is known as
a) data cycle
b) regain cycle
c) retain cycle
d) refresh cycle
Explanation: The data storage in RAM which is capacitance (reverse-biased diode) may have a leakage current that tends to discharge the capacitor giving rise to possibility of data loss. To avoid this, the data must be refreshed after a fixed time interval regularly.
6. The field in which dynamic RAM is more complicated than static RAM is
b) interfacing circuit
c) execution unit
Explanation: The refresh mechanism and the additional hardware required makes the interfacing circuit of dynamic RAM more complicated than that of static RAM.
7. Memory refresh activity is
a) initialised by processor
b) initialised by external bus master
c) initialised by refresh mechanism
d) initialised either by processor or by external bus
Explanation: The refresh operation is independent regular activity that is initialised and carried out by the refresh mechanism.
8. The number of memory chips that are enabled at a time for refresh activity is
d) more than 1
Explanation: More than one memory chip can be enabled at a time to refresh activity to reduce the number of total memory refresh cycles.
9. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is
a) constant timer
b) data managing timer
c) refresh timer
d) qualitative timer
Explanation: Refresh timer derives a pulse for refreshing action after each refresh interval which can be qualitatively defined as the time for which a dynamic RAM cell can hold data charge level practically constant.
10. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as
Explanation: Refresh time is the ratio of time duration taken for refreshing to the number of rows that are refreshed. Refresh frequency is the reciprocal of refresh time.
Sanfoundry Global Education & Learning Series – Microprocessors.