Microprocessors Questions and Answers – DMA Transfers and Operations

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “DMA Transfers and Operations”.

1. The 8257 is able to accomplish the operation of
a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned
View Answer

Answer: d
Explanation: The 8257 can accomplish three types of operations and they are
i) verify DMA operation
ii) write operation
iii) read operation.

2. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned
View Answer

Answer: b
Explanation: If the HLDA signal is received by the DMA controller, it indicates that the bus is available.

3. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK (active low)
d) DACK (active high)
View Answer

Answer: c
Explanation: The DACK (active low) line of the used channel is pulled down by the DMA controller to indicate the I/O device that its request for the DMA transfer has been honored by the CPU.
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4. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned
View Answer

Answer: c
Explanation: If more than one channel requests service simultaneously, then the transfer occurs as a burst or continuous transfer.

5. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK (active low)
c) DACK (active high)
d) HLDA
View Answer

Answer: d
Explanation: The burst or continuous transfer may be interrupted by an external device by pulling down the HLDA line.

6. The number of clock cycles required for an 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned
View Answer

Answer: b
Explanation: The 8257 uses four clock cycles to complete a transfer.

7. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to be in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
View Answer

Answer: b
Explanation: In this scheme, the DRQ3 has the lowest priority followed by DRQ2 and DRQ1. The DRQ0 has the highest priority.
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8. The priority of the channels varies frequently in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned
View Answer

Answer: a
Explanation: In this scheme, the priorities assigned to the channels are not fixed.

9. The register of 8257 that can only be written in is
a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register
View Answer

Answer: c
Explanation: The selected register may be read or written depending on the instruction executed by the CPU. But only write operation can be performed on the mode set register.
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10. The operation that can be performed on the status register is
a) write operation
b) read operation
c) read and write operations
d) none of the mentioned
View Answer

Answer: b
Explanation: The status register can only be read.

Sanfoundry Global Education & Learning Series – Microprocessors.

Here’s the list of Best Books in Microprocessors.

To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice Questions and Answers.

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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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