Microprocessors Questions and Answers – Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction

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This set of Microprocessors online test focuses on “Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction”.

1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned
View Answer

Answer: c
Explanation: The salient feature of Pentium is its superscalar, superpipelined architecture.
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2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6
View Answer

Answer: b
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage pipeline.

3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned
View Answer

Answer: b
Explanation: The Pentium has two separate caches. They are data cache and instruction cache.

4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned
View Answer

Answer: c
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage pipeline. This enhances the speed of integer arithmetic of Pentium to a large extent.

5. For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned
View Answer

Answer: b
Explanation: For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of multiple instruction issue.
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6. Which of the following is a class of architecture of MII (multiple instruction issue)?
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture
View Answer

Answer: d
Explanation: The MII architecture may again be classified into two categories:
1. Very long instruction word architecture
2. Superscalar architecture.

7. The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
View Answer

Answer: c
Explanation: In VLIW processors, the compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group, and issues them in parallel for execution.

8. The architecture in which the hardware decides which instructions are to be issued concurrently at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) superscalar architecture
View Answer

Answer: d
Explanation: In the superscalar architecture, the hardware decides which instructions are to be issued concurrently at run time.

9. The CPU has to wait until the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned
View Answer

Answer: b
Explanation: In conditional branch, the CPU has to wait until the execution stage to determine whether the condition is met or not. When the condition satisfies, a branch is to be taken.
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10. The memory device that holds branch target addresses for previously executed branches is
a) Tristate buffer
b) RAM
c) ROM
d) Branch target buffer
View Answer

Answer: d
Explanation: The branch target buffer in Pentium CPU holds branch target addresses for previously executed branches.

11. The branch target buffer is
a) four-way set-associative memory
b) has branch instruction address
c) has destination address
d) all of the mentioned
View Answer

Answer: d
Explanation: The branch target buffer is a four-way set-associative memory. Whenever a branch is taken, the CPU enters the branch instruction address, and also the destination address in the branch target buffer.

Sanfoundry Global Education & Learning Series – Microprocessors.

Here’s the list of Best Reference Books in Microprocessors.

To practice all areas of Microprocessors for online tests, here is complete set of 1000+ Multiple Choice Questions and Answers.
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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn