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Microprocessors Multiple Choice Questions | MCQs | Quiz

Microprocessor Interview Questions and Answers
Pratice Microprocessor questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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•   Machine Language Formats
•   8086 Addressing Modes
•   8086/8088 Instruction Set-1
•   8086/8088 Instruction Set-2
•   8086/8088 Instruction Set-3
•   Assembler Directives
•   Instructions Do's & Don'ts
•   Assembler Programming
•   Stack
•   8086/8088 Stack Structure
•   Interrupt Service Routines
•   8086/8088 Interrupt Cycle
•   Non Maskable Interrupt
•   Interrupt Programming
•   Macros
•   Timings & Delays
•   Semiconductor Interfacing
•   Dynamic RAM Interfacing
•   Interfacing I/O Ports
•   PIO 8255
•   8255 Operation Modes
•   Analog - Digital Converters
•   Stepper Motor Interfacing
•   8254 Interval Timer
•   8259A Interrupt Controller
•   8279 Keyboard Controller
•   8251 USART
•   8257 DMA Controller
•   DMA Transfer & Operations
•   8237 DMA Interface - 1
•   8237 DMA Interface - 2
•   High Storage Capacity
•   Interconnection Topologies
•   Software Aspects
•   Numeric Processor 8087 - 1
•   Numeric Processor 8087 - 2
•   8089 I/O Processor
•   Bus Arbitration & Control
•   Tightly Coupled Systems
•   Multi Microprocessor
•   80286 Salient Features
•   80286 Internal Architecture
•   80286 Signal Descriptions
•   Real Addressing Mode
•   PVAM - 1
•   PVAM - 2
•   Privilege
•   Protection
•   Special Operations
•   80286 System Configuration
•   Bus Hold & HLDA
•   Instruction Set Features - 1
•   Instruction Set Features - 2
•   80287 Math Coprocessor-1
•   80287 Math Coprocessor-2
•   80386DX Salient Features
•   ↓ 80386 ↓
•   Architecture & Signals
•   Register Organisation - 1
•   Register Organisation - 2
•   80386 Data Types
•   80386 Real Address Mode
•   Segmentation
•   Paging
•   80387 Coprocessor
•   80386 Instruction Set
•   80486DX Coprocessor
•   80586 (Pentium) Features
•   System Architecture
•   Intel MMX Architecture
•   MMX Data Types
•   MMX Instruction Set
•   Pentium-Pro & Pentium2 - 1
•   Pentium-Pro & Pentium2 - 2
•   Pentium 4 Features - 1
•   Pentium 4 Features - 2
•   Hyperthreading Technology
•   Pentium Hyperthreading
•   Formal Verification
•   Hybrid Architecture - 1
•   Hybrid Architecture - 2
•   8051 Architecture
•   8051 Register Set
•   8051 Interrupt & Stack - 1
•   8051 Interrupt & Stack - 2
•   8051 Addressing Modes
•   8051 Instruction Set - 1
•   8051 Instruction Set - 2
•   8051 Ports Interfacing - 1
•   8051 Ports Interfacing - 2
•   8051 Interrupt Structure
•   Serial Communication Unit
•   Power Control Register

Best Reference Books

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Microprocessors Questions and Answers – Pentium – Pro and Pentium-II -1

Posted on March 18, 2014 by Manish

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Pentium – Pro and Pentium-II -1”.

1. The instructions that pass through the fetch, decode and execution stages sequentially is known as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
View Answer

Answer: c
Explanation: The linear instruction sequencing is the one in which the instructions that pass through the fetch, decode and execution stages sequentially.

2. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) cpu
View Answer

Answer: b
Explanation: During the execution of instructions, only after the bus interface unit of CPU reads the data from the main memory and returns it to the register, the next instruction execution will commence.

3. Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
a) 1
b) 2
c) 3
d) 4
View Answer

Answer: b
Explanation: Pentium’s superscalar architecture employs five stage pipeline with U and V pipes. Thus it can execute two instructions per clock.

4. The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
View Answer

Answer: a
Explanation: The speculative execution is an execution which means that the CPU should speculate which of the next instructions can be executed earlier.

5. The execution in which the consecutive instruction execution in a sequential flow is hampered is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
View Answer

Answer: b
Explanation: In the out of turn execution, the consecutive instruction execution in a sequential flow is hampered and the CPU should be able to execute out of turn instructions.

6. A dual independent bus has
a) Enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) High throughput
d) All of the mentioned
View Answer

Answer: d
Explanation: A dual independent bus architecture is incorporated by Pentium-Pro to get an enhanced system bandwidth and it also yields high throughput. It has the CPU which can access both main memory and the cache simultaneously.

7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
View Answer

Answer: c
Explanation: The processor uses an associative memory called branch target buffer for implementing the algorithm, multiple branch prediction.

8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit
View Answer

Answer: c
Explanation: Pentium-Pro incorporates three independent engines, 1. Fetch-decode unit 2. Dispatch-execute unit 3. Retire unit.

9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
View Answer

Answer: a
Explanation: The fetch-decode unit accepts the sequence of instructions from the instruction cache as input and then decodes them.

10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
a) 1
b) 2
c) 3
d) 4
View Answer

Answer: c
Explanation: A set of three parallel decoders accepts the stream of fetched instructions and decode them.

Sanfoundry Global Education & Learning Series – Microprocessors.

Here’s the list of Best Reference Books in Microprocessors.

To practice all areas of Microprocessors, here is complete set of 1000+ Multiple Choice Questions and Answers.
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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer and SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage & Cluster Administration, Advanced C Programming, SAN Storage Technologies, SCSI Internals and Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him below:
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