This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Pentium – Pro and Pentium-II -1”.
1. The instructions that pass through the fetch, decode and execution stages sequentially is known as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
View Answer
Explanation: The linear instruction sequencing is the one in which the instructions that pass through the fetch, decode and execution stages sequentially.
2. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) cpu
View Answer
Explanation: During the execution of instructions, only after the bus interface unit of CPU reads the data from the main memory and returns it to the register, the next instruction execution will commence.
3. Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: Pentium’s superscalar architecture employs five stage pipeline with U and V pipes. Thus it can execute two instructions per clock.
4. The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
View Answer
Explanation: The speculative execution is an execution which means that the CPU should speculate which of the next instructions can be executed earlier.
5. The execution in which the consecutive instruction execution in a sequential flow is hampered is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
View Answer
Explanation: In the out of turn execution, the consecutive instruction execution in a sequential flow is hampered and the CPU should be able to execute out of turn instructions.
6. A dual independent bus has
a) Enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) High throughput
d) All of the mentioned
View Answer
Explanation: A dual independent bus architecture is incorporated by Pentium-Pro to get an enhanced system bandwidth and it also yields high throughput. It has the CPU which can access both main memory and the cache simultaneously.
7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
View Answer
Explanation: The processor uses an associative memory called branch target buffer for implementing the algorithm, multiple branch prediction.
8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit
View Answer
Explanation: Pentium-Pro incorporates three independent engines, 1. Fetch-decode unit 2. Dispatch-execute unit 3. Retire unit.
9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
View Answer
Explanation: The fetch-decode unit accepts the sequence of instructions from the instruction cache as input and then decodes them.
10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: A set of three parallel decoders accepts the stream of fetched instructions and decode them.
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