This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “System Architecture”.
1. The stage in which the CPU fetches the instructions from the instruction cache in superscalar organization is
a) Prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) Final stage
View Answer
Explanation: In the prefetch stage of pipeline, the CPU fetches the instructions from the instruction cache, which stores the instructions to be executed. In this stage, CPU also aligns the codes appropriately.
2. The CPU decodes the instructions and generates control words in
a) Prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) Final stage
View Answer
Explanation: In D1 stage, the CPU decodes the instructions and generates control words. For simple RISC instructions, only single control word is enough for starting the execution.
3. The fifth stage of pipeline is also known as
a) read back stage
b) read forward stage
c) write back stage
d) none of the mentioned
View Answer
Explanation: The fifth stage or final stage of pipeline is also known as “Write back (WB) stage”.
4. In the execution stage the function performed is
a) CPU accesses data cache
b) executes arithmetic/logic computations
c) executes floating point operations in execution unit
d) all of the mentioned
View Answer
Explanation: In the execution stage, known as E-stage, the CPU accesses data cache, executes arithmetic/logic computations, and floating point operations in execution unit.
5. The stage in which the CPU generates an address for data memory references in this stage is
a) prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) execution stage
View Answer
Explanation: In the D2 (second decode) stage, CPU generates an address for data memory references in this stage. This stage is required where the control word from D1 stage is again decoded for final execution.
6. The feature of separated caches is
a) supports the superscalar organization
b) high bandwidth
c) low hit ratio
d) all of the mentioned
View Answer
Explanation: The separated caches have low hit ratio compared to a unified cache, but have the advantage of supporting the superscalar organization and high bandwidth.
7. In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from
a) floating point unit
b) instruction cache
c) floating point register file or data cache
d) floating point register file or instruction cache
View Answer
Explanation: In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from either floating point register file or data cache.
8. The FPU (Floating Point Unit) writes the results to the floating point register file in
a) X1 execution state
b) X2 execution state
c) write back stage
d) none of the mentioned
View Answer
Explanation: In the two execution stages of X1 and X2, the floating point unit reads the data from the data cache and executes the floating point computation. In the “write back stage” of pipeline, the FPU (Floating Point Unit) writes the results to the floating point register file.
9. The floating point multiplier segment performs floating point multiplication in
a) single precision
b) double precision
c) extended precision
d) all of the mentioned
View Answer
Explanation: The floating point multiplier segment performs floating point multiplication in single precision, double precision and extended precision.
10. The instruction or segment that executes the floating point square root instructions is
a) floating point square root segment
b) floating point division and square root segment
c) floating point divider segment
d) none of the mentioned
View Answer
Explanation: The floating point divider segment executes the floating point division and square root instructions.
11. The floating point rounder segment performs rounding off operation at
a) after write back stage
b) before write back stage
c) before arithmetic operations
d) none of the mentioned
View Answer
Explanation: The results of floating point addition or division process may be required to be rounded off, before write back stage to the floating point registers.
12. Which of the following is a floating point exception that is generated in case of integer arithmetic?
a) divide by zero
b) overflow
c) denormal operand
d) all of the mentioned
View Answer
Explanation: In the case of integer arithmetic, the possible floating point exceptions in Pentium are:
1. divide by zero
2. overflow
3. denormal operand
4. underflow
5. invalid operation.
13. The mechanism that determines whether a floating point operation will be executed without creating any exception is
a) Multiple Instruction Issue
b) Multiple Exception Issue
c) Safe Instruction Recognition
d) Safe Exception Recognition
View Answer
Explanation: A mechanism known as Safe Exception Recognition (SER) had been employed in Pentium which determines whether a floating point operation will be executed without creating any exception.
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