Microprocessors Questions and Answers – I/O Processor 8089

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This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “I/O Processor 8089”.

1. The 8089 shares the system bus and memory with the host CPU in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
View Answer

Answer: a
Explanation: In a tightly coupled configuration, the 8089 shares the system bus and memory with the host CPU using its RQ (active low) or GT (active low) pins.
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2. The 8089 communicates with the host CPU using bus arbiter and controller in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
View Answer

Answer: b
Explanation: In a loosely coupled configuration, the 8089 has its own local bus and communicates with the host CPU using bus arbiter and controller.

3. The number of address lines used by the I/O processor in 8089 is
a) 20
b) 12
c) 16
d) 8
View Answer

Answer: c
Explanation: The 8089 I/O processor uses only 16 address lines, and thus it can address only 64KB of IO space.

4. The IO device that can be interfaced with 8089 is
a) 16-bit IO
b) 8-bit IO
c) 64-bit IO
d) 16-bit and 8-bit IO
View Answer

Answer: d
Explanation: The 8089 handled IO devices need not have the same data bus width as that of 8089. This enables even 8-bit IO devices to be interfaced easily with 8089.

5. In the 8089 architecture, the address of memory table for channel-2 is calculated by
a) adding 16 to the contents of CCP
b) adding 8 to the contents of CCP
c) adding memory table address of channel-1
d) none of the mentioned
View Answer

Answer: b
Explanation: The address of the memory table for channel-2 is calculated by adding 8 to the contents of CCP or by adding memory table address for channel-1 to the contents of CCP.
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6. Which of the following is not a general purpose register of 8089?
a) GA
b) BC
c) CX
d) MC
View Answer

Answer: c
Explanation: The registers GA, GB, GC, BC, IX and MC can be used as general purpose registers.

7. The registers that are used as source and destination pointers during DMA operations are
a) GB, GC
b) GC, BC
c) GC, GA
d) GA, GB
View Answer

Answer: d
Explanation: GA register is used as source and GB as destination pointers during DMA operations.

8. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ (active low) or GT (active low)
View Answer

Answer: c
Explanation: The DRQ and EXT are used for data transfer control and operation termination signals during DMA operations.

9. The pin that is used to inform the CPU that the previous operation is completed is
a) RQ (active low)
b) GT (active low)
c) DRQ
d) SINTR
View Answer

Answer: d
Explanation: The SINTR pins are used by the channels either to inform the CPU that the previous operation is over or to ask for its attention or interference if required, before the completion of the task.

10. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned
View Answer

Answer: d
Explanation: The program status word contains the current channel status, which contains source and destination address widths, channel activity, interrupt control and servicing, bus load limit and priority information.
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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn