# Microprocessors Questions and Answers – Enhanced Instruction Set of Pentium, Intel MMX Architecture

This set of Tricky Microprocessors Questions and Answers focuses on “Enhanced Instruction Set of Pentium, Intel MMX Architecture”.

1. Which of the following is not a transcendental instruction?
a) FSIN
b) FCOS
c) FMUL
d) FPTAN

Explanation: The FMUL instruction is a float point multiplication, which is not a transcendental instruction.

2. The transcendental instruction that supports computation of sine and cosine is
a) FCOSSIN
b) FSNE
c) FSINFCOS
d) FSINCOS

Explanation: The instruction, FSINCOS, supports to compute sine and cosine.

3. The instruction that computes tan(x) is
a) FTAN
b) FTNGNT
c) FPTAN
d) FXTAN

Explanation: The instruction, FPTAN, computes tan(x).

4. The instruction that computes arctan(x) is
a) FTAN
b) FACTN
c) FARCTAN
d) FPATAN

Explanation: The instruction, FPATAN, computes arctan(x) which is arc tangent of x.

5. The instruction, F2XMI, is used to compute
a) 2X
b) 2X-1
c) 2X+1
d) 2X+2

Explanation: The instruction, F2XMI, is used to compute 2X-1.
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6. The instruction, FYL2XP, supports to compute the expression
a) Y*logX
b) Y*log2X
c) Y*log(2X+1)
d) Y*log2(X+1)

Explanation: The instruction, FYL2XP, supports to compute the expression Y*log2(X+1).

7. The size of a general purpose floating point register of floating point unit is
a) 4 bytes
b) 40 bytes
c) 8 bytes
d) 80 bits

Explanation: There are eight general purpose floating point registers in the floating point unit. Each of these eight registers are of 80-bits width.

8. For floating point operations, the bits used by mantissa in a floating point register is
a) 32
b) 64
c) 72
d) 79

Explanation: For floating point operations, 64 bits are used for the mantissa, and the rest 16 bits for exponent.

9. The multimedia applications mainly require the architecture of
a) single instruction stream single data stream
b) multiple instruction stream single data stream
c) single instruction stream multiple data stream
d) multiple instruction stream multiple data stream

Explanation: Most of the multimedia applications mainly require the architecture of single instruction stream multiple data stream.

10. The size of each MMX (Multimedia Extension) register is
a) 32 bits
b) 64 bits
c) 128 bits
d) 256 bits

Explanation: The MMX registers use only the 64-bit mantissa portion of the general purpose floating point registers, to store MMX operands. Thus, the MMX programmers virtually get eight new MMX registers, each of 64 bits.

11. After a sequence of MMX instructions is executed, the MMX registers should be cleared by an instruction,
a) CLEAR
b) RESET
c) EMM
d) EMMS

Explanation: After a sequence of MMX instructions is executed, the MMX registers should be cleared by an instruction, EMMS, which implies Empty the MMX Stack.

12. The number of pixels that can be manipulated in a single register by the CPU using MMX architecture is
a) 4
b) 6
c) 8
d) 10

Explanation: Any CPU can manipulate only one pixel at a time. But by using MMX architecture, we can manipulate eight such pixels, packed in a single 64-bit register.

13. After executing the floating point instructions, the floating point registers should be cleared by an instruction,
a) CLEAR
b) EFPR
c) EMMF
d) EMMS

Explanation: After executing the floating point instructions, the floating point registers should be cleared by an instruction, EMMS.

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