This set of 8051 Micro-controller Multiple Choice Questions & Answers (MCQs) focuses on “Interrupt Programming”.
1. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
View Answer
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vector table that holds the address of the Interrupt Service Routine.
2. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
View Answer
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or the contents of the IE register becomes null.
3. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
View Answer
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is stored when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instructions.
4. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
View Answer
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low leveled pulse.
5. Which bit of the IE register is used to enable TxD/RxD interrupt?
a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
View Answer
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.
6. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
View Answer
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enable all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled interrupts.
7. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
View Answer
Explanation: There is a small space of memory present in the vector table between two different interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is available.
8. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
View Answer
Explanation: TCON register is used to make any interrupt level or edge triggered.
9. What is the disadvantage of a level triggered pulse?
a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
View Answer
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it will be generating another interrupt.
10. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
View Answer
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote highest priority.
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