This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Protection”.
1. The mechanism to provide protection, that is accomplished with the help of read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
View Answer
Explanation: The restricted use of segments is accomplished with the help of read/write privileges.
2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Explanation: In restricted use of segments i.e. segment load check, the segment usages are restricted by classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
View Answer
Explanation: Restricted accesses to segment, also called, operation reference check, is accomplished using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels, determined by CPL (Current Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
View Answer
Explanation: The privileged instructions or operations, also called, privileged instruction check, is executed at certain privilege levels, determined by CPL and I/O privilege level(IOPL), as defined by the flag register.
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
View Answer
Explanation: The IRET and POPF instructions do not perform any of their functions, if CPL is not of the required privilege level.
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
View Answer
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for this condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
View Answer
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions, LIDT, LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
View Answer
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS, OUT, STI, CLI and LOCK.
9. The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
View Answer
Explanation: At the ESC instruction, the exception is generated, but the processor extension registers contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
View Answer
Explanation: The processor extension segment overrun has no error code on the stack.
11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
View Answer
Explanation: Double exception detected, invalid task state segment, stack segment overrun, processor extension segment overrun, are the protected mode exceptions.
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