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Microprocessors Multiple Choice Questions | MCQs | Quiz

Microprocessor Interview Questions and Answers
Practice Microprocessor questions and answers for interviews, campus placements, online tests, aptitude tests, quizzes and competitive exams.

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•   Machine Language Formats
•   8086 Addressing Modes
•   8086/8088 Instruction Set-1
•   8086/8088 Instruction Set-2
•   8086/8088 Instruction Set-3
•   Assembler Directives
•   Instructions Do's & Don'ts
•   Assembler Programming
•   Stack
•   8086/8088 Stack Structure
•   Interrupt Service Routines
•   8086/8088 Interrupt Cycle
•   Non Maskable Interrupt
•   Interrupt Programming
•   Macros
•   Timings & Delays
•   Semiconductor Interfacing
•   Dynamic RAM Interfacing
•   Interfacing I/O Ports
•   PIO 8255
•   8255 Operation Modes
•   Analog - Digital Converters
•   Stepper Motor Interfacing
•   8254 Interval Timer
•   8259A Interrupt Controller
•   8279 Keyboard Controller
•   8251 USART
•   8257 DMA Controller
•   DMA Transfer & Operations
•   8237 DMA Interface - 1
•   8237 DMA Interface - 2
•   High Storage Capacity
•   Interconnection Topologies
•   Software Aspects
•   Numeric Processor 8087 - 1
•   Numeric Processor 8087 - 2
•   8089 I/O Processor
•   Bus Arbitration & Control
•   Tightly Coupled Systems
•   Multi Microprocessor
•   80286 Salient Features
•   80286 Internal Architecture
•   80286 Signal Descriptions
•   Real Addressing Mode
•   PVAM - 1
•   PVAM - 2
•   Privilege
•   Protection
•   Special Operations
•   80286 System Configuration
•   Bus Hold & HLDA
•   Instruction Set Features - 1
•   Instruction Set Features - 2
•   80287 Math Coprocessor-1
•   80287 Math Coprocessor-2
•   80386DX Salient Features
•   ↓ 80386 ↓
•   Architecture & Signals
•   Register Organisation - 1
•   Register Organisation - 2
•   80386 Data Types
•   80386 Real Address Mode
•   Segmentation
•   Paging
•   80387 Coprocessor
•   80386 Instruction Set
•   80486DX Coprocessor
•   80586 (Pentium) Features
•   System Architecture
•   Intel MMX Architecture
•   MMX Data Types
•   MMX Instruction Set
•   Pentium-Pro & Pentium2 - 1
•   Pentium-Pro & Pentium2 - 2
•   Pentium 4 Features - 1
•   Pentium 4 Features - 2
•   Hyperthreading Technology
•   Pentium Hyperthreading
•   Formal Verification
•   Hybrid Architecture - 1
•   Hybrid Architecture - 2
•   8051 Architecture
•   8051 Register Set
•   8051 Interrupt & Stack - 1
•   8051 Interrupt & Stack - 2
•   8051 Addressing Modes
•   8051 Instruction Set - 1
•   8051 Instruction Set - 2
•   8051 Ports Interfacing - 1
•   8051 Ports Interfacing - 2
•   8051 Interrupt Structure
•   Serial Communication Unit
•   Power Control Register

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Microprocessors Questions and Answers – Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design Issues of RISC Processors -1

Posted on March 18, 2014 by Manish

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design Issues of RISC Processors -1”.

1. The disadvantage of CISC design processors is
a) low burden on compiler developers
b) wide availability of existing software
c) complex in nature
d) none
View Answer

Answer: c
Explanation: Some computers are used in preference to CISC design due to its low burden on compiler developers and wide availability of existing software. But they are complex in nature.
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2. The RISC architecture is preferred to CISC because RISC architecture has
a) simplicity
b) efficiency
c) high speed
d) all of the mentioned
View Answer

Answer: d
Explanation: The RISC architecture is preferred to CISC because RISC architecture is simple, highly efficient and the processors using RISC architecture have high speed.

3. The feature of RISC that is not present in CISC is
a) branch prediction
b) pipelining
c) branch prediction and pipelining
d) none
View Answer

Answer: c
Explanation: A RISC core allows performance enhancing features, such as branch prediction and pipelining. Traditionally, these have only been possible in RISC designs.

4. The feature of hybrid CISC-RISC architecture is
a) consume a lot of power
b) not applicable to mobile applications
c) processed by RISC core
d) all of the mentioned
View Answer

Answer: d
Explanation: The CISC-RISC hybrids continue to consume a lot of power and are not best candidates for mobile and embedded applications.

5. Which of the following is an application of RISC architecture by adding more instructions?
a) multimedia applications
b) telecommunication encoding
c) image conversion
d) all of the mentioned
View Answer

Answer: d
Explanation: By adding more instructions to the RISC architecture, some applications can be run much faster like multimedia applications, telecommunication encoding/decoding, image conversion and video processing.
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6. Which of the following processor belongs to hybrid RISC-CISC architecture?
a) Intel Pentium III
b) Intel Itanium 64
c) AMD’s X86-64
d) All of the mentioned
View Answer

Answer: d
Explanation: The processors, Intel Pentium III, Intel Itanium 64 and AMD’s X86-64 consists of hybrid RISC-CISC architecture.

7. In order to implement complex instructions, CISC architectures use
a) macroprogramming
b) hardwire
c) microprogramming
d) none
View Answer

Answer: c
Explanation: In order to implement complex instructions, CISC architectures use microprogramming.

8. The advantage of RISC processors is
a) can operate at high clock frequency
b) shorter design cycle
c) simple and fast
d) all of the mentioned
View Answer

Answer: d
Explanation: The advantages of RISC processors are that they can work at high clock frequency, can be designed, developed and tested more quickly with a high speed.

9. The additional functionality that can be placed on the same chip of RISC is
a) Memory management units
b) Floating point units
c) Memory management and floating point arithmetic units
d) RAM, ROM
View Answer

Answer: c
Explanation: Several extra functionalities, such as memory management units or floating point arithmetic units, can also be placed on the same chip of RISC.

10. The number of clockcycles that take to wait until the length of the instruction is known in order to start decoding is
a) 0
b) 1
c) 2
d) 3
View Answer

Answer: a
Explanation: The loading and decoding the instructions in a RISC processor is simple and fast. It is not needed to wait until the length of the instruction is known in order to start the decoding.
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Microprocessors Questions and Answers – Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design Issues of RISC Processors -2 »
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Manish Bhojasia
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He is Linux Kernel Developer & SAN Architect and is passionate about competency developments in these areas. He lives in Bangalore and delivers focused training sessions to IT professionals in Linux Kernel, Linux Debugging, Linux Device Drivers, Linux Networking, Linux Storage, Advanced C Programming, SAN Storage Technologies, SCSI Internals & Storage Protocols such as iSCSI & Fiber Channel. Stay connected with him @ LinkedIn | Facebook | Twitter

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