This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Programmable Interrupt Controller 8259A”.
1. The number of hardware interrupts that the processor 8085 consists of is
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather an external device was supposed to hand over the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the direction of the Priority Resolver.
4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Explanation: The interrupt control logic performs all the operations that are involved within the interrupts like accepting and managing interrupt acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored interrupts can be provided.
6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to designate whether the chip is used as a master or a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR.
9. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
Explanation: The automatic rotation is used in the applications where all the interrupting devices are of equal priority.
Sanfoundry Global Education & Learning Series – Microprocessors.