# Sequential Logic Design Questions and Answers – Modeling Registers and Counters Using VHDL Processes – Set 2

This set of Sequential Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Modeling Registers and Counters Using VHDL Processes – Set 2”.

1. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 4 bit wide synchronous up counter which has a reset. The reset is active HIGH and synchronous. The clock is clk, the input is reset, and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset: in std_logic;
q: out std_logic_vector(3 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
begin
process (clk) begin
if rising_edge(clk) then
if reset = '1' then
Q <= "0000";
else
Q <= Q + 1;
end if;
end if;
end process;
end behaviour;```

c)

```architecture behaviour of reg is
begin
process (clk) begin
if rising_edge(clk) then
if reset = '1' then
Q <= "0000";
else
Q <= Q - 1;
end if;
end if;
end process;
end behaviour;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
else
tmp <= tmp + 1;
end if;
end if;
end process;
end;```
Explanation:
This is the state table of a synchronous counter with synchronous reset, all changes occur on the positive edge of the clock.

Reset Qn+1
1 0
0 Qn

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

2. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 4 bit wide synchronous up counter which has an enable input and a reset. The enable input is active HIGH and synchronous. The reset input is active HIGH and synchronous. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset, enable: in std_logic;
q: out std_logic_vector(3 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
q <= (others => '0');
elsif enable = '1' then
q <= q + 1;
end if;
end if;
end process;
end;```

c)

```architecture synth of counter is
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
q <= (others => '0');
elsif enable = '1' then
q <= q + 1;
end if;
end if;
end process;
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
end;```
Explanation:
This is the state table of a synchronous counter with synchronous reset and enable, all changes occur on the positive edge of the clock.

Reset Enable Qn+1
1 x 0
0 1 Qn+1
0 0 Qn

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

3. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 4 bit wide synchronous up counter which has a reset. The reset is active LOW and synchronous. The clock is clk, the input is reset, and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset: in std_logic;
q: out std_logic_vector(3 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
begin
process (clk) begin
if rising_edge(clk) then
if reset = '1' then
Q <= "0000";
else
Q <= Q + 1;
end if;
end if;
end process;
end behaviour;```

c)

```architecture behaviour of reg is
begin
process (clk) begin
if rising_edge(clk) then
if reset = '0' then
Q <= "0000";
else
Q <= Q + 1;
end if;
end if;
end process;
end behaviour;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous counter with synchronous reset, all changes occur on the positive edge of the clock. The reset is active LOW.

Reset Qn+1
0 0
1 Qn

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

4. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 4 bit wide synchronous up counter which has an enable input and a reset. The enable input is active LOW and synchronous. The reset input is active HIGH and synchronous. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset, enable: in std_logic;
q: out std_logic_vector(3 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
elsif enable = '0' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
q <= (others => '0');
elsif enable = '0' then
q <= q + 1;
end if;
end if;
end process;
end;```

c)

```architecture synth of counter is
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
q <= (others => '0');
elsif enable = '0' then
q <= q + 1;
end if;
end if;
end process;
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous counter with synchronous reset and enable, all changes occur on the positive edge of the clock. The enable input is active LOW.

Reset enable Qn+1
1 x 0
0 0 Qn+1
0 1 Qn

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

5. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 4 bit wide synchronous loadable up counter which has a reset. The reset is active HIGH and synchronous. The load is active HIGH and synchronous. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
d: in std_logic_vector(3 downto 0);
q: out std_logic_vector(3 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
tmp <= unsigned(d);
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
q <= (others => '0');
q <= unsigned(d);
else
q <= q + 1;
end if;
end if;
end process;
end;```

c)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= d;
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= unsigned(d);
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous counter with synchronous Load and reset, all changes occur on the positive edge of the clock.

1 x 0
0 1 D
0 0 Qn+1

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

6. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 4 bit wide synchronous up counter which has an enable input and a reset. The enable input is active HIGH and synchronous. The reset input is active HIGH and asynchronous. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset, enable: in std_logic;
q: out std_logic_vector(3 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk, reset) begin
if reset = '1' then
tmp <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

c)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk, reset) begin
if reset = '1' then
tmp <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk, reset) begin
if reset = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
q <= q + 1;
end if;
end if;
end process;
end;```
Explanation:
This is the state table of a synchronous counter with synchronous enable and asynchronous reset. The reset and enable are active HIGH.

Reset clock enable Qn+1
1 x x 0
0 1 Qn+1
0 0 Qn

Based on this table the VHDL code is written.

7. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 8 bit wide synchronous up counter which has a reset. The reset is active LOW and synchronous. The clock is clk, the input is reset, and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset: in std_logic;
q: out std_logic_vector(7 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(7 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
begin
process (clk) begin
if rising_edge(clk) then
if reset = '1' then
Q <= "0000";
else
Q <= Q + 1;
end if;
end if;
end process;
end behaviour;```

c)

```architecture behaviour of reg is
begin
process (clk) begin
if rising_edge(clk) then
if reset = '0' then
Q <= "0000";
else
Q <= Q + 1;
end if;
end if;
end process;
end behaviour;```

d)

```architecture synth of counter is
signal tmp: unsigned(7 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous counter with synchronous reset, all changes occur on the positive edge of the clock. The reset is active LOW.

Reset Qn+1
0 0
1 Qn+1

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

8. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 16 bit wide synchronous loadable up counter which has a reset. The reset is active LOW and synchronous. The load is active LOW and synchronous. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
d: in std_logic_vector(15 downto 0);
q: out std_logic_vector(15 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= unsigned(d);
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
signal tmp: unsigned(16 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
q <= (others => '0');
q <= unsigned(d);
else
q <= q + 1;
end if;
end if;
end process;
end;```

c)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= d;
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= unsigned(d);
else
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous counter with synchronous Load and reset, all changes occur on the positive edge of the clock. The reset and Load are active LOW.

0 x 0
1 0 D
1 1 Qn+1

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

9. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 16 bit wide synchronous loadable up counter which has a reset and enable. The reset is active LOW and synchronous. The load is active LOW and synchronous. The enable is active HIGH and synchronous. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset, load, enable: in std_logic;
d: in std_logic_vector(15 downto 0);
q: out std_logic_vector(15 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

c)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '0' then
tmp <= tmp + 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous counter with synchronous Load, reset and enable. All changes occur on the positive edge of the clock. The reset and Load are active LOW.

0 x x 0
0 0 x D
1 1 1 Qn+1
1 1 0 Qn

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

10. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 16 bit wide synchronous loadable up/down counter which has a reset, enable and dir input. The reset is active LOW and synchronous. The load is active LOW and synchronous. The enable is active HIGH and synchronous. The counter counts upwards if dir is HIGH, else it counts downwards. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset, load, enable, dir: in std_logic;
d: in std_logic_vector(15 downto 0);
q: out std_logic_vector(15 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
q <= (others => '0');
q <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
q <= q + 1;
else
q <= q - 1;
end if;
end if;
end if;
end process;
end;```

c)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '0' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '0' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of a synchronous up/down counter with synchronous Load, reset and enable. All changes occur on the positive edge of the clock. The reset and Load are active LOW.

0 x x x 0
1 0 x x D
1 1 0 x Qn
1 1 1 1 Qn+1
1 1 1 0 Qn-1

Based on this table the VHDL code is written. Unsigned type is used in the process since the std_logic_vector type does not support the addition operator.

11. Write a synthesizable VHDL architecture for the given VHDL entity of a positive edge triggered 16 bit wide synchronous loadable up/down counter which has a reset, enable and dir input. The reset is active HIGH and asynchronous. The load is active HIGH and synchronous. The enable is active HIGH and synchronous. The counter counts upwards if dir is HIGH, else it counts downwards. The clock is clk and there is a single output Q. Assume that the IEEE library, std_logic_1164 package of IEEE library and numeric_std package of IEEE library are included.

```entity counter is
port(clk, reset, load, enable, dir: in std_logic;
d: in std_logic_vector(15 downto 0);
q: out std_logic_vector(15 downto 0));
end;```

a)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk, reset) begin
if reset = '1' then
tmp <= (others => '0');
elsif rising_edge(clk) then
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

b)

```architecture synth of counter is
signal tmp: unsigned(15 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
if reset = '1' then
tmp <= (others => '0');
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```

c)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk, reset) begin
if reset = '1' then
tmp <= (others => '0');
elsif rising_edge(clk) then
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end if;
end process;
end;```

d)

```architecture synth of counter is
signal tmp: unsigned(3 downto 0);
begin
process(clk, reset) begin
if reset = '1' then
tmp <= (others => '0');
elsif rising_edge(clk) then
tmp <= unsigned(d);
elsif enable = '1' then
if dir = '1' then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end process;
q <= std_logic_vector(tmp);
end;```
Explanation:
This is the state table of an up/down counter with synchronous enable and load. The load and enable are active HIGH. The reset is active HIGH and asynchronous.

Reset Clock Load Enable Dir Qn+1
1 x x x x 0
0 1 x x D
0 0 0 x Qn
0 0 1 1 Qn+1
0 0 1 0 Qn-1

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