Sequential Logic Design Questions and Answers – Modeling Registers and Counters Using VHDL Processes

This set of Sequential Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Modeling Registers and Counters Using VHDL Processes”.

1. Write the VHDL behavioural code of a positive edge triggered 4 bit wide register which has a reset and a load input. The reset and load are synchronous and active HIGH. The clock is clk, the inputs are D, reset and load, and there is a single output Q. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(4 downto 0);
    Q: out std_logic_vector(4 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

c)

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entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '0' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '0' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a register with synchronous Load and reset, all changes occur on the positive edge of the clock

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Reset Load Q
0 x 0000
1 1 D
1 0 Previous state

Based on this table the VHDL code is written.



2. Write the VHDL behavioural code of a positive edge triggered 4 bit wide register which has a reset and a load input. The load is synchronous and active HIGH. The reset is asynchronous and active HIGH. The clock is clk, the inputs are D, reset and load, and there is a single output Q. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk, reset) begin
    if reset = '1' then
        Q <= "0000";
    elsif rising_edge(clk) then
        if load = '1' then   
            Q <= D;
        end if;
   end if;
end process;
end behaviour;

b)

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entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
 
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk, reset) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if reset = '0' then
        Q <= "0000";
    elsif load = '1' then   
        Q <= D;
    end if;
    end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a register with synchronous Load and asynchronous reset.

Reset Clock Load Q
1 x x 0000
0 ↑ 1 D
0 ↑ 0 Previous state

Based on this table the VHDL code is written.



3. Write the VHDL behavioural code of a positive edge triggered 4 bit wide register which has a reset and a load input. The reset and load are synchronous. The reset is active LOW and the Load is active HIGH. The clock is clk, the inputs are D, reset and load, and there is a single output Q. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(4 downto 0);
    Q: out std_logic_vector(4 downto 0));
end entity reg;
 
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '0' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '0' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;
View Answer
Answer: d
Explanation: This is the state table of a register with synchronous Load and reset, all changes occur on the positive edge of the clock. The reset is active LOW.

Reset Load Q
0 x 0000
1 1 D
1 0 Previous state

Based on this table the VHDL code is written.



4. Write the VHDL behavioural code of a positive edge triggered 4 bit wide register which has a reset and a load input. The reset and load are synchronous. The reset is active HIGH and the Load is active LOW. The clock is clk, the inputs are D, reset and load, and there is a single output Q. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(4 downto 0);
    Q: out std_logic_vector(4 downto 0));
end entity reg;
 
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '0' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '0' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;
View Answer
Answer: c
Explanation:
This is the state table of a register with synchronous Load and reset, all changes occur on the positive edge of the clock. The Load is active LOW.

Reset Load Q
0 x 0000
0 0 D
0 1 Previous state

Based on this table the VHDL code is written.



5. Write the VHDL behavioural code of a positive edge triggered 4 bit wide register which has a reset and a load input. The reset and load are synchronous and active LOW. The clock is clk, the inputs are D, reset and load, and there is a single output Q. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '0' then
            Q <= "0000";
        elsif load = '0' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(4 downto 0);
    Q: out std_logic_vector(4 downto 0));
end entity reg;
 
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '1' then
            Q <= "0000";
        elsif load = '0' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk) begin
    if rising_edge(clk) then
        if reset = '0' then
            Q <= "0000";
        elsif load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a register with synchronous Load and reset, all changes occur on the positive edge of the clock

Reset Load Q
0 x 0000
1 0 D
1 1 Previous state

Based on this table the VHDL code is written.



6. Write the VHDL behavioural code of a positive edge triggered 4 bit wide register which has a reset and a load input. The load is synchronous and active HIGH. The reset is asynchronous and active LOW. The clock is clk, the inputs are D, reset and load, and there is a single output Q. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk, reset) begin
    if reset = '0' then
        Q <= "0000";
    elsif rising_edge(clk) then
        if load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk, reset) begin
    if reset = '1' then
        Q <= "0000";
    elsif rising_edge(clk) then
        if load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk, reset) begin
    if reset = '1' then
        Q <= "0000";
    elsif rising_edge(clk) then
        if load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process (clk, reset) begin
    if reset = '0' then
        Q <= "0000";
    elsif rising_edge(clk) then
        if load = '1' then   
            Q <= D;
        end if;
    end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a register with synchronous Load and asynchronous reset. The reset is active LOW.

Reset Clock Load Q
0 x x 0000
1 ↑ 1 D
1 ↑ 0 Previous state

Based on this table the VHDL code is written.



7. Write the VHDL code for a 4-bit left shift register with synchronous reset and load. The clock is clk, the inputs are R_in, D, reset, left_shift and load, and there is a single output Q. Reset, left_shift and load are active HIGH. The register shifts the output bits to the left when left_shift is enabled, by concatenating the 3 rightmost bits of Q with R_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '1' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk, reset)
begin
if rising_edge(clk) then
    if reset = '1' then Q <= "0000";
    elsif load = '1' then Q <= not(D);
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '0' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '0' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '0' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a left shift register with synchronous Load, reset and left_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock.

Reset Load left_shift Q3 Q2 Q1 Q0
1 x x 0 0 0 0
0 1 x D3 D2 D1 D0
0 0 1 Q2 Q1 Q0 R_in
0 0 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



8. Write the VHDL code for a 4-bit left shift register with asynchronous reset, synchronous load. The clock is clk, the inputs are R_in, D, reset, left_shift and load, and there is a single output Q. Reset, left_shift and load are active HIGH. The register shifts the output bits to the left when left_shift is enabled, by concatenating the 3 rightmost bits of Q with R_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '1' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk, reset)
begin
if rising_edge(clk) then
    if reset = '1' then Q <= "0000";
    elsif load = '1' then Q <= not(D);
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '0' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '0' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '0' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;
View Answer
Answer: b
Explanation:
This is the state table of a left shift register with synchronous Load, asynchronous reset and left_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock.

Reset Clock Load left_shift Q3 Q2 Q1 Q0
1 x x x 0 0 0 0
0 ↑ 1 x D3 D2 D1 D0
0 ↑ 0 1 Q2 Q1 Q0 R_in
0 ↑ 0 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



9. Write the VHDL code for a 4-bit left shift register with asynchronous reset, synchronous load. The clock is clk, the inputs are R_in, D, reset, left_shift and load, and there is a single output Q. Reset, left_shift and load are active HIGH. The register shifts the output bits to the left when left_shift is enabled, by concatenating the 3 rightmost bits of Q with R_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '1' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk, reset)
begin
if rising_edge(clk) then
    if reset = '1' then Q <= "0000";
    elsif load = '1' then Q <= not(D);
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '0' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
    if reset = '0' then Q <= "0000";
    elsif load = '1' then Q <= D;
    elsif left_shift = '0' then Q <= Q(2 downto 0) & R_in;
    end if;
end if;
end process;
end behaviour;
View Answer
Answer: b
Explanation:
This is the state table of a left shift register with synchronous Load, asynchronous reset and left_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock.

Reset Clock Load left_shift Q3 Q2 Q1 Q0
0 x x x 0 0 0
1 ↑ 1 x D3 D2 D1 D0
1 ↑ 1 1 Q2 Q1 Q0 R_in
1 ↑ 0 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



10. Write the VHDL code for a 4-bit left shift register with synchronous reset and load. The clock is clk, the inputs are R_in, D, reset, left_shift and load, and there is a single output Q. Left_shift and Reset are active HIGH. Load is active LOW. The register shifts the output bits to the left when left_shift is enabled, by concatenating the 3 rightmost bits of Q with R_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '1' then Q <= not(D);
elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif left_shift = '1' then Q <= Q(2 downto 0) & R_in;
end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, left_shift, R_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif left_shift = '0' then Q <= Q(2 downto 0) & R_in;
end if;
end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a left shift register with synchronous Load, reset and left_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock. Load is active LOW.

Reset Load left_shift Q3 Q2 Q1 Q0
1 x x 0 0 0 0
0 0 x D3 D2 D1 D0
0 1 1 Q2 Q1 Q0 R_in
0 1 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



11. Write the VHDL code for a 4-bit right shift register with synchronous reset and load. The clock is clk, the inputs are L_in, D, reset, right_shift and load, and there is a single output Q. Reset, right_shift and load are active HIGH. The register shifts the output bits to the right when right_shift is enabled, by concatenating the 3 leftmost bits of Q with L_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
 
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a right shift register with synchronous Load, reset and right_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock.

Reset Load right_shift Q3 Q2 Q1 Q0
1 x x 0 0 0 0
0 1 x D3 D2 D1 D0
0 0 1 L_in Q3 Q2 Q1
0 0 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



12. Write the VHDL code for a 4-bit right shift register with synchronous reset and load. The clock is clk, the inputs are L_in, D, reset, right_shift and load, and there is a single output Q. Right_shift and load are active HIGH. Reset is active LOW. The register shifts the output bits to the right when right_shift is enabled, by concatenating the 3 leftmost bits of Q with L_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;
View Answer
Answer: b
Explanation:
This is the state table of a right shift register with synchronous Load, reset and right_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock. The reset is active LOW.

Reset Load right_shift Q3 Q2 Q1 Q0
0 x x 0 0 0 0
1 1 x D3 D2 D1 D0
1 0 1 L_in Q3 Q2 Q1
1 0 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



13. Write the VHDL code for a 4-bit right shift register with synchronous reset and load. The clock is clk, the inputs are L_in, D, reset, right_shift and load, and there is a single output Q. Reset and load are active LOW. Right_shift is active HIGH. The register shifts the output bits to the right when right_shift is enabled, by concatenating the 3 leftmost bits of Q with L_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;
View Answer
Answer: d
Explanation:
This is the state table of a right shift register with synchronous Load, reset and right_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock. The reset and load are active LOW.

Reset Load right_shift Q3 Q2 Q1 Q0
0 x x 0 0 0 0
1 0 x D3 D2 D1 D0
1 1 1 L_in Q3 Q2 Q1
1 1 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



14. Write the VHDL code for a 4-bit right shift register with synchronous reset and load. The clock is clk, the inputs are L_in, D, reset, right_shift and load, and there is a single output Q. Reset and Right_shift are active HIGH. Load is active LOW. The register shifts the output bits to the right when right_shift is enabled, by concatenating the 3 leftmost bits of Q with L_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;
View Answer
Answer: c
Explanation:
This is the state table of a right shift register with synchronous Load, reset and right_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock. The load is active LOW.

Reset Load right_shift Q3 Q2 Q1 Q0
1 x x 0 0 0 0
0 0 x D3 D2 D1 D0
0 1 1 L_in Q3 Q2 Q1
0 1 0 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.



15. Write the VHDL code for a 4-bit right shift register with synchronous reset and load. The clock is clk, the inputs are L_in, D, reset, right_shift and load, and there is a single output Q. Reset, right_shift and load are active LOW. The register shifts the output bits to the right when right_shift is enabled, by concatenating the 3 leftmost bits of Q with L_in. Assume that the IEEE library and std_logic_1164 package are included.
a)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '0' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

b)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
 
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '1' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

c)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;

d)

entity reg is
port (clk, reset, load, right_shift, L_in: in std_logic;
    D: in std_logic_vector(3 downto 0);
    Q: out std_logic_vector(3 downto 0));
end entity reg;
architecture behaviour of reg is 
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then Q <= "0000";
elsif load = '0' then Q <= D;
elsif right_shift = '1' then Q <= L_in & Q(3 downto 1);
end if;
end if;
end process;
end behaviour;
View Answer
Answer: a
Explanation:
This is the state table of a right shift register with synchronous Load, reset and right_shift. Q3 and D3 are the Most Significant Bits of the output and parallel load input, respectively. All transitions occur on the rising edge of the clock. Load, reset and right_shift are active LOW.

Reset Load right_shift Q3 Q2 Q1 Q0
0 x x 0 0 0 0
1 0 x D3 D2 D1 D0
1 1 0 L_in Q3 Q2 Q1
1 1 1 Previous state Previous state Previous state Previous state

Based on this table the VHDL code is written.


Sanfoundry Global Education & Learning Series – Logic Design.

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If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]

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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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