# Digital Circuits Questions and Answers – Asynchronous Counter

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Asynchronous Counter”.

1. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32

Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

2. A ripple counter’s speed is limited by the propagation delay of _____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates

Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

3. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications

Explanation: One of the major drawbacks to the use of asynchronous counters is that High-frequency applications are limited because of internal propagation delays. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

4. Internal propagation delay of asynchronous counter is removed by ____________
a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter

Explanation: Propagation delay refers to the amount of time taken in producing an output when the input is altered. Internal propagation delay of asynchronous counter is removed by synchronous counter because clock input is given to each flip-flop individually in synchronous counter.

5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2

Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st flip-flop is given to second flip-flop as clock input. So, in case of binary down counter the output word decreases by 1.
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6. How many flip-flops are required to construct a decade counter?
a) 4
b) 8
c) 5
d) 10

Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n. 24=16and23=8, therefore, 4 flip flops needed.

7. The terminal count of a typical modulus-10 binary counter is ____________
a) 0000
b) 1010
c) 1001
d) 1111

Explanation: A binary counter counts or produces the equivalent binary number depending on the cycles of the clock input. Modulus-10 means count from 0 to 9. So, the terminal count is 9 (1001).

8. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16

Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.

9. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns

Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 = 60ns.

10. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
a) 1
b) 2
c) 8
d) 15

Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore, transition states = 24 – 1 = 15. So, total transitional states are 15.

11. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns

Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 = 60.

12. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000

13. A ripple counter’s speed is limited by the propagation delay of ____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates

Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

14. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16

Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

15. A principle regarding most display decoders is that when the correct input is present, the related output will switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW

Explanation: A principle regarding most display decoders is that when the correct input is present, the related output will switch LOW. Since it’s an active-low device.

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