# Digital Circuits Questions and Answers – Asynchronous Down Counter

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Asynchronous Down Counter”.

1. Which of the following statements are true?
a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock

Explanation: Asynchronous events does not occur at the same time because of propagation delay and they do need a clock pulse to trigger them. Whereas, synchronous events occur in presence of clock pulse.

2. A down counter using n-flip-flops count ______________
a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count

Explanation: As the name suggests down counter means counting occurs from a higher value to lower value (i.e. (2^n – 1) to 0).

3. UP Counter is ____________
a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
d) Toggles between Up and Down count

Explanation: UP counter counts in an upward manner from 0 to (2n – 1).

4. DOWN counter is ____________
a) It counts in upward manner
b) It count in downward manner
c) It counts in both the direction
d) Toggles between Up and Down count

Explanation: DOWN counter counts in a downward manner from (2n – 1) to 0.

5. How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8

Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.
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6. In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop goes from HIGH to LOW.
a) MSB flip-flop
b) LSB flip-flop
c) Master slave flip-flop
d) Latch

Explanation: Since the LSB flip-flop changes its state at each negative transition of clock. That is why LSB flip-flop doesn’t have toggle.

7. In a 3-bit asynchronous down counter, the initial content is ____________
a) 000
b) 111
c) 010
d) 101

Explanation: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first negative transition of the clock, the counter content becomes 101.

8. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
a) 000
b) 111
c) 101
d) 010

Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 111.

9. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
a) 000
b) 111
c) 101
d) 010

Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 101.

10. The hexadecimal equivalent of 15,536 is ________
a) 3CB0
b) 3C66
c) 63C0
d) 6300

Explanation: You just divide the number by 16 at the end and store the remainder from bottom to top.

11. In order to check the CLR function of a counter ____________
a) Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling

Explanation: CLR stands for clearing or resetting all states of flip-flop. In order to check the CLR function of a counter, apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state.

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