This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “RISC Processor”.
1. Which are the processors based on RISC?
Explanation: SPARC and MIPS processors are the first generation processors of RISC architecture.
2. What is 80/20 rule?
a) 80% instruction is generated and 20% instruction is executed
b) 80% instruction is executed and 20% instruction is generated
c) 80%instruction is executed and 20% instruction is not executed
d) 80% instruction is generated and 20% instructions are not generated
Explanation: 80% of instructions are generated and only 20% of the instruction set is executed that is, by simplifying the instructions, the performance of the processor can be increased which lead to the formation of RISC that is reduced instruction set computing.
3. Which of the architecture is more complex?
Explanation: SPARC have RISC architecture which has a simple instruction set but MC68020, MC68030, 8086 have CISC architecture which is more complex than CISC.
4. Which is the first company who defined RISC architecture?
Explanation: In 1970s IBM identified RISC architecture.
5. Which of the following processors execute its instruction in a single cycle?
d) MIPS R2000
Explanation: MIPS R2000 possess RISC architecture in which the processor executes its instruction in a single clock cycle and also synthesize complex operations from the same reduced instruction set.
6. How is memory accessed in RISC architecture?
a) load and store instruction
b) opcode instruction
c) memory instruction
d) bus instruction
Explanation: The data of memory address is loaded into a register and manipulated, its contents are written out to the main memory.
7. Which of the following has a Harvard architecture?
Explanation: PIC follows Harvard architecture in which the external bus architecture consist of separate buses for instruction and data whereas SSEM, EDSAC, CSIRAC are stored program architecture.
8. Which of the following statements are true for von Neumann architecture?
a) shared bus between the program memory and data memory
b) separate bus between the program memory and data memory
c) external bus for program memory and data memory
d) external bus for data memory only
Explanation: von Neumann architecture shares bus between program memory and data memory whereas Harvard architecture have a separate bus for program memory and data memory.
9. What is CAM stands for?
a) content-addressable memory
b) complex addressable memory
c) computing addressable memory
d) concurrently addressable memory
Explanation: Non-von Neumann architecture is based on content-addressable memory.
10. Which of the following processors uses Harvard architecture?
a) TEXAS TMS320
Explanation: It is a digital signal processor which have small and highly optimized audio or video processing signals. It possesses multiple parallel data bus.
11. Which company further developed the study of RISC architecture?
c) university of Berkeley
Explanation: The University of Berkeley and Stanford university provides the basic architecture model of RISC.
12. Princeton architecture is also known as
a) von Neumann architecture
Explanation: The von Neumann architecture is also known as von Neumann model or Princeton architecture.
13. Who coined the term RISC?
a) David Patterson
b) von Neumann
c) Michael J Flynn
Explanation: David Patterson of Berkeley university coined the term RISC whereas Michael J Flynn who first views RISC.
14. Which of the following is an 8-bit RISC Harvard architecture?
d) Motorola 6800
Explanation: AVR is an 8-bit RISC architecture developed by Atmel. Zilog80, 8051, Motorola 6800 are having CISC architectures.
15. Which of the following processors has CISC architecture?
d) Zilog Z80
Explanation: Zilog80 have CISC architecture whereas AVR, Atmel and blackfin possess RISC architecture.
Sanfoundry Global Education & Learning Series – Embedded System.
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