This set of Sequential Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Processes and Sequential Statements”.
1. Which one of the following keyword is used to define a process in VHDL?
a) “process”
b) “proc”
c) “pr”
d) “pro”
View Answer
Explanation: An alternative form for a process uses wait statements instead of a sensitivity list. A process cannot have both a wait statement and a sensitivity list. Any process in VHDL can be defined as “process”.
2. Which of the following is the function of “wait” statement of VHDL?
a) To take a short break from the program
b) To wait until any subroutine specified is completed
c) To terminate the program
d) To redirect the direction flow of the program to another direction
View Answer
Explanation: Any process will execute a sequential-statements until a wait statement is encountered. Then, it will wait until the specified wait condition is satisfied. It will then execute the next set of sequential-statements until another wait is encountered.
3. Which one of the following is not a right syntax of wait statement?
a) Wait on
b) Wait for
c) Wait until
d) Wait at
View Answer
Explanation: Any process will execute sequential-statements until a wait statement is encountered. Then, it will wait until the specified wait condition is satisfied. It will then execute the next set of sequential-statements until another wait is encountered. Wait statements can be of three different forms – wait on, wait for and wait until. Wait at is not a correct statement.
4. In which part of a VHDL code, the components are declared?
a) Process
b) Architecture
c) Entity
d) Begin
View Answer
Explanation: The components can only be declared after entity declaration. Thus component can be declared either in architecture or in package. If they are declared in package, then just include the package. No need to declare it again.
5. The wait statement “wait until” uses which type of data type?
a) BIT
b) BIT_VECTOR
c) Integer
d) Boolean
View Answer
Explanation: Any process will execute sequential-statements until a wait statement is encountered. Then, it will wait until the specified wait condition is satisfied. It will then execute the next set of sequential-statements until another wait is encountered. The “wait until” statement operates on Boolean type variable. They can be True or False and the condition is fulfilled when it’s True.
6. The wait statement “wait on” uses which type of data type?
a) BIT
b) BIT_VECTOR
c) Sensitivity-list
d) Boolean
View Answer
Explanation: Until a wait statement is encountered, any process will execute sequential-statements. It will then execute the next set of sequential-statements until another wait is encountered. The “wait on” statement operates on sensitivity-list. It will wait until one variable from the sensitivity list changes.
7. If any entity is defined as inout it can be both read and written.
a) True
b) False
View Answer
Explanation: In the entity section, we define the pin descriptions of the various pins used. Descriptions can be of various types – in, out, inout, buffer. The inout description is used for the oins those can be used both as input and outputs.
8. What is the effect of the following VHDL code?
wait until A = B</b>
a) The program flow will wait for any random time interval
b) The program will wait until A is equal to B
c) The program will give an error report if A is not equal to B
d) The program will be terminated if A is not equal to B
View Answer
Explanation: The “wait until” statement operates on Boolean type variable. They can be True or False and the condition is fulfilled when it’s True. This program will wait until either A or B changes. Then, A B is evaluated, and if the result is TRUE, the process will continue, or else the process will continue to wait until A or B changes again and A B is TRUE.
9. Which of the following is a conditional statement for VHDL?
a) Entity
b) Wait
c) If
d) Process
View Answer
Explanation: The “if” statement is used to check any condition in VHDL. So it is a conditional statement. Entity, wait and process have another functions. However, if and case statements are always sequential, yet conditional signal assignment statements and selected signal assignment statements can only be concurrent.
10. What is the function of the “wait” statement of the following VHDL code?
Process begin C A and B after 5 ns; E C or D after 5 ns; wait on A, B, C, D; end process;
a) Waits for all of A, B, C, D to change
b) Waits until any one of A, B, C, D sets to TRUE
c) Replaces the sensitivity list at the beginning
d) Terminated the code snippet
View Answer
Explanation: process will execute sequential-statements until a wait statement is encountered. Then, it will wait until the specified wait condition is satisfied. The wait statement at the end of the process replaces the sensitivity list at the beginning. In this way both processes will initially execute the sequential statements one time and, then, wait until A, B, C, or D changes.
Sanfoundry Global Education & Learning Series – Logic Design.
To practice all areas of Logic Design, here is complete set of 1000+ Multiple Choice Questions and Answers.
