This set of Linear Integrated Circuit Multiple Choice Questions & Answers (MCQs) focuses on “Monolithic Phase-Locked Loop”.
1. What is the conversion ratio of the phase detector in 565 PLL?
Explanation: The conversion ratio of the phase detector of 565 PLL (Monolithic PLL) Kφ = 1.4/π = 0.4458.
2. Given fo = 1.2kHz and V = 13v, find the lock-in range of monolithic Phase-Locked Loop.
Explanation: The lock-in range of monolithic PLL, △fL = ±(7.8×fo)/V = ±(7.8×1.2kHz)/13 = ±720Hz.
3. Find out the incorrect statement.
Monolithic phase detector is preferred for critical applications as it is:
1. Independent of variation in amplitude
2. Independent of variation in duty cycle of the input waveform
3. Independent of variation in response time
a) 1 & 2
b) 1 & 3
c) 2 & 3
d) 1, 2 & 3
Explanation: Monolithic phase detectors are not sensitive to harmonics of the input signal and change in duty cycle of input and output frequency.
4. Determine the capture range of IC PLL 565 for a lock-in range of ± 1kHz.
a) △fc = ±31.453Hz
b) None of the mentioned
c) △fc = ±87.653Hz
d) △fc = ±66.505Hz
Explanation: The capture range is △fc = ±[△fL/ (2π×3.6×103×C]0.5 = ±[1kHz/(2π×3.6×kΩ×10µF)]0.5 = ±[1kHz/226.08×-6]0.5 = 0.5 = ±66.505Hz.
5. Find the lock-in range of monolithic Phase-Locked Loop from the given diagram.
a) -fo-△fL to fo-△fL
b) -fo-△fL to -fo-△fC
c) fo-△fL to fo-△fC
d) -fo-△fC to fo-△fC
Explanation: Lock-in range of monolithic PLL is from -fo-△fL to fo-△fL.
Sanfoundry Global Education & Learning Series – Linear Integrated Circuit.