Linear Integrated Circuit Questions and Answers – Input Offset Voltage – 3

This set of Linear Integrated Circuit Questions and Answers for Campus interviews focuses on “Input Offset Voltage – 3”.

1. What happens if R1>>RF in the circuit

2. Determine the voltage gain for the circuit.
Determine the voltage gain for the given circuit
a) 1.1
b) 1.6
c) 1.2
d) 2.2
View Answer

Answer: d
Explanation: The voltage gain, AF={1+[RF/( R1+ Rc)]} = 1+[15kΩ/(2.5kΩ+10kΩ)] = 2.2.

3. Where does the compensating network connected in an inverting amplifier.
a) Non-inverting input terminal
b) Inverting input terminal
c) Between non-inverting and output terminal
d) Between inverting and output terminal
View Answer

Answer: a
Explanation: The offset voltage compensating network is connected in the non-inverting terminal for the inverting amplifier and vice versa.
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4. Why closed loop differential amplifiers are difficult to null?
a) Due to compensating network
b) Due to feedback loop
c) Due to input offset voltage
d) None of the mentioned
View Answer

Answer: a
Explanation: The closed loop differential amplifiers are more difficult to null because the use of compensating network can change the common mode rejection mode.

5. How to achieve maximum CMRR in the given circuit?
Find the maximum CMRR from the given circuit
a) R1 = RF
b) RF = R3|| RC+ RB and R1= R2
c) R1= R2 and RF= R3+ RC
d) None of the mentioned
View Answer

Answer: c
Explanation: To achieve maximum CMRR in the circuit the value of R1= R2 and RF= R3+ RC.
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6. What is the advantage of compensated differential amplifier?
a) All of the mentioned
b) Slightly complex circuit
c) Does not affect CMRR
d) Balanced op-amp
View Answer

Answer: d
Explanation: Since the compensated differential amplifier uses the op-amp with offset voltage null pins. The offset null circuit does not affect the CMRR.

7. The offset voltage in the voltage follower is balanced using
a) Voltage drop across the load resistor
b) Voltage drop across feedback resistor
c) Compensating network connected to inverting input terminal
d) Compensating network connected to non- inverting input terminal
View Answer

Answer: b
Explanation: Voltage drop across the feedback resistor connect to inverting input terminal is used to cancel the offset voltage in voltage follower.
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8. Find the maximum possible output offset voltage, which is caused by the input offset voltage Vio=15mv?
Find the maximum possible output offset voltage, which is caused by the input offset voltage
a) 0.075v
b) 0.75v
c) 0.75v
d) 7.5v
View Answer

Answer: a
Explanation: Aoo=[1+(RF/R1)] =1+(10kΩ/2.5kΩ) = 5.
Voo=5*15mv = 75mv.

9. Compute the output voltage for voltage follower with offset voltage compensating network?
Compute the output voltage for the voltage follower with offset voltage compensating network
a) 3.6v
b) 10.8v
c) 26v
d) 33v
View Answer

Answer: b
Explanation: The output voltage is given as Vo= {1+[ RC/( Rb+ (Rmax/4))]}*Vin.
Rmax=Ra/4 = 20kΩ/4 = 5kΩ.
Vo=[1+(39kΩ/(10kΩ+5kΩ))]*3v = 10.8v.
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Sanfoundry Global Education & Learning Series – Linear Integrated Circuits.

To practice all areas of Linear Integrated Circuit for Campus Interviews, here is complete set of 1000+ Multiple Choice Questions and Answers.

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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