# Linear Integrated Circuit Questions and Answers – A to D Converter – 2

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This set of Linear Integrated Circuit Multiple Choice Questions & Answers (MCQs) focuses on “A to D Converter -2”.

1. At what condition the digital to analog conversion is made? a) Va > Vd
b) Va ≤ Vd
c) Va ≥ Vd
d) Va ≠ Vd

Explanation: When Va < Vd, the output of the comparator becomes low and the AND gate is disabled. This stops the counting at that time and the digital output of the counter represents the analog input voltage.

2. If a input at Va is 1010, then find the correct conversion sequence for the given circuit.
a)

 Input signal SAR output at different stages comparator output 1010 1000 1 1100 0 1010 1 1011 0 1010

b)

 Input signal SAR output at different stages comparator output 1010 0001 0 0010 1 0011 0 1010 1
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c)

 Input signal SAR output at different stages comparator output 1010 1111 0 1011 0 1001 1 1010 1

d) None of the mentioned

Explanation: The given circuit is a successive approximation register and it finds the required value of each bit trial and error method. When the conversion start SAR set MSB d1=1 with other bits zero. So, trial code is 1000. If Va(1010) is greater than DAC output (1000). Then MSB is left `1′ and the next lower significant bit is made `1′ and further tested.

3. The Integrating type converters are used in
a) Digital meter
b) Panel meter
c) Monitoring system
d) All of the mentioned

Explanation: The Integrating type converters are used in application such as digital meter, panel meter and monitoring system where the conversion accuracy is critical.

4. In integrating type ADCs, the
a) Input voltage is proportional to input averaged over the integration period
b) Output voltage is proportional to input averaged over the integration period
c) Output voltage is proportional to sum of input voltage
d) Input voltage is proportional to sum of input voltage

Explanation: Since the integrating type ADC do not require sample and hold circuit at the input. The change in input during conversion will not affect the output code and is proportional to the value of the input averaged over the integration period.

5. Which type of ADC is chosen for noisy environment?
b) Dual slope
d) All of the mentioned

Explanation: The main advantage of these converters is that it is possible to transmit frequency even in noisy environment or in isolated form.

6. How to overcome the drawback of the charge balancing ADC?
a) By using precision integrator
b) By using Voltage to frequency converter
c) By using voltage comparator
d) By using dual slope converter

Explanation: Charge balancing ADC depend up on RC product whose value cannot be easily maintained with temperature and time. This is eliminated using dual slope ADC as it is independent of R, C and T.

7. Which among the following has long conversion time?
a) Servo converter
b) Dual ramp converter
c) Flash converter
d) None of the mentioned

Explanation: The main disadvantage of dual slope ADC is the long conversion time. For instance, if 2n-T=1/50 is used to reject line pick-up, the conversion time will be 20ms.

8. In which application dual slop converter are used.
a) Thermocouple
b) Digital panel meter
c) Weighting scale
d) All of the mentioned

Explanation: Dual slope converters are particularly suitable for accurate measurement of slow varying signals.

9. A dual slope has the following specifications:
16bit counter; Clock rate =4 MHz; Input voltage=12v; Output voltage =-7v and Capacitor=0.47µF.
If the counters have cycled through 2n counts, determine the value of resistor in the integrator.
a) 60kΩ
b) 50kΩ
c) 120kΩ
d) 100kΩ

Explanation: Time period of the dual slope integrator,
△(t) =t2-t1 =2ncounts/clock rate =216/4Mhz=16.38ms.
For integration,
△Vo=(-1/RC)×V×( t2-t1)
=> RC = -(12v/-7v) ×16.38ms=28.08ms
∴ R= 28.08ms =59744 ≅60kΩ.

10. A 12 bit dual ramp generation has a maximum output voltage of +12v. Compute the equivalent digital number for the analog signal of +6v.
a) 1000000000
b) 10000000000
c) 1000000000000
d) 100000000000

Explanation: since Va =VR (N/2n) so the digital count N= 2n×(Va/VR)
N= 212×(6/12v) = 4096×0.5 =2048.
Binary equivalent for 2048 => 100000000000.

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