# Logic Design Questions and Answers – VHDL – Packages, Libraries and IEEE Standard Logic

This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “VHDL – Packages, Libraries and IEEE Standard Logic”.

1. The package and its associated compiled VHDL models may be placed in a library.
a) True
b) False

Explanation: The package and its associated compiled VHDL models may be placed in a library, so they can be accessed as required by different VHDL designs. A VHDL library is used so that the VHDL code can be reused easily.

2. The IEEE Standard library 1164 defines a std_logic type that has 8 values.
a) True
b) False

Explanation: The IEEE Standard library 1164 defines a std_logic type that has 9 values: ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’ and ‘–’. The answer is False, because std_logic has 9 and not 8 values.

3. In the IEEE Standard library 1164 std_logic type, what does the value ‘U’ stand for?
a) Uninitialized
b) Undefined
c) Unknown
d) Unsigned

Explanation: The ‘U’ value stands for uninitialized. When a logic circuit is first turned on, the signals will be uninitialized. If these signals are represented by std_logic, they will have a value of ‘U’ until they are updated.

4. What is a group of std_logic signals represented as?
a) std_logic_vector
b) vector_std_logic
c) logic_vector
d) bit_vector

Explanation: A group of std_logic signals is represented by a std_logic_vector. For example to declare a 4 bit wide std_logic_vector A, use

`signal A: std_logic_vector(3 downto 0);`

5. In the IEEE Standard library 1164 std_logic type, what does the value ‘Z’ stand for?
a) High-Impedance
b) Signed number
c) Signed bit
d) Integer

Explanation: The value ‘Z’ is called the high-impedance value, and represents the condition of a signal source when that source makes no effective contribution to the resolved value of the signal. High impedance value is used in bus-systems of computers.

6. In the IEEE Standard library 1164 std_logic type, what does the value ‘–’ stand for?
a) Don’t care
b) Unsigned number
c) Signed bit
d) Negative integer

Explanation: The value ‘–’ is also called the don’t care value. It is used for wildcard matching. When used inside conditions, it means the ‘–’ can stand for 0 or 1.

7. When an uninitialized signal is connected to any other signal, what is the result?
a) ‘U’ – Uninitialized
b) ‘–’ – Don’t care
c) ‘1’
d) ‘0’

Explanation: When an uninitialized signal is connected to any other signal, VHDL evaluates the result to be uninitialized. This is a rule defined by the VHDL standard.

8. In the IEEE Standard library 1164 std_logic type, what does the value ‘X’ stand for?
a) Unknown value
b) Unsigned number
c) Signed bit
d) Integer

Explanation: The value ‘X’ stands for unknown value. If a std_logic / std_logic_vector type signal is assigned conflicting values during simulation, then it will be set to ‘X’. This is so that in simulation one can know that the behaviour is undefined.

9. Consider a signal of type std_logic or std_logic_vector. If it assigned conflicting values during simulation, what will it be set to?
a) ‘U’ – Uninitialized
b) ‘–’ – Don’t care
c) ‘X’ – Unknown
d) ‘0’

Explanation: The value ‘X’ stands for unknown value. If a std_logic / std_logic_vector type signal is assigned conflicting values during simulation, then it will be set to ‘X’. This is done to inform the one who is simulating that the behaviour would be undefined.

10. Which EDA company originally developed the std_logic_unsigned package?
a) Synopsys
b) Mentor Graphics
d) Xilinx

Explanation: Synopsys originally developed the std_logic_unsigned package. The std_logic_unsigned package defines arithmetic operators (+, −, *) and comparison operators (<, <=, =, /=, >, >=) that operate on std_logic_vectors.

11. In VHDL, the code needs to be compiled before simulating.
a) True
b) False

Explanation: Before the VHDL model of a digital system can be simulated, the VHDL code must first be compiled. The VHDL compiler, also called an analyzer, first checks the VHDL source code to see that it conforms to the syntax and semantic rules of VHDL.

12. VHDL statements execute concurrently.
a) True
b) False

Explanation: VHDL statements execute concurrently so that it can model real hardware in which components are all in operation all the same time. VHDL is a hardware description language, and statements are executed concurrently, unlike statements in programming languages like C which execute sequentially.

Sanfoundry Global Education & Learning Series – Logic Design.

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