This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Design of Binary Counters”.
1. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk) begin if (reset) q <= 4'b0000; else if (en) q <= q + 1; end endmodule
a) 4 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and asynchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit synchronous Up counter. If the reset signal becomes HIGH, the counter resets to 0000. Therefore the reset is active HIGH. The reset is synchronous since the counter can reset only on the positive edge of the clock. If the enable signal becomes HIGH, the counter starts counting up from 0000 to 1111. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 1111 is 0000.
2. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk) begin if (reset) q <= 4'b0000; else if (en) q <= q - 1; end endmodule
a) 4 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit Down counter. If the reset signal becomes HIGH, the counter resets to 0000. So the reset is active HIGH. The reset is synchronous since the counter will reset can on the positive edge of the clock. If the enable signal becomes HIGH, the counter starts counting down from 1111 to 0000. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 0000 is 1111 .
3. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock output reg [3:0] q; always @ (posedge clk or posedge reset) begin if (reset) q <= 4'b0000; else if (en) q <= q + 1; end endmodule
a) 4 bit synchronous up counter with asynchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit synchronous Up counter. If the reset signal becomes HIGH, the counter resets to 0000. Therefore the reset is active HIGH. The reset is asynchronous since it is independent of the clock. If the enable signal becomes HIGH, the counter starts counting up from 0000 to 1111. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 1111 is 0000.
4. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk or posedge reset) begin if (reset) q <= 4'b0000; else if (en) q <= q - 1; end endmodule
a) 4 bit synchronous down counter with asynchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
c) 3 bit asynchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit Down counter. If the reset signal becomes HIGH, the counter resets to 0000. So the reset is active HIGH. The reset is asynchronous since it is independent of the clock. If the enable signal becomes HIGH, the counter starts counting down from 1111 to 0000. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 0000 is 1111.
5. Write the Verilog code for a Modulus 99 up counter.
a)
module dut(clk, q); input clk; //clock signal output reg [6:0] q; //output always @ (posedge clk) begin if (q == 98) q <= 0; else q <= q + 1; end endmodule
b)
module dut(clk, q); input clk; //clock signal output reg [6:0] q; //output always @ (posedge clk) begin if (q == 99) q <= 0; else q <= q + 1; end endmodule
c)
module dut(clk, q); input clk; //clock signal output reg [4:0] q; //output always @ (posedge clk) begin if (q == 98) q <= 0; else q <= q + 1; end endmodule
d)
module dut(clk, q); input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk) begin if (q == 98) q <= 0; else q <= q + 1; end endmodule
Explanation: A Modulus N counter has N states. Since the counter starts counting from 0, the counter has to reset to zero when it reaches N-1. Here N = 99, so the counter has to reset to 0 when it reaches 98. Since it has to store 98, which is equal to 1100010 in binary it needs 7 digits. So the output register has to be 7 bits wide.
6. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk or posedge reset) begin if (reset) q <= 4'b0000; else if (en) q <= q - 1; end endmodule
a) 4 bit synchronous down counter with asynchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
c) 3 bit asynchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit Down counter. If the reset signal becomes HIGH, the counter resets to 0000. So the reset is active HIGH. The reset is asynchronous since it is independent of the clock. If the enable signal becomes HIGH, the counter starts counting down from 1111 to 0000. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 0000 is 1111 .
7. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk) begin if (!reset) q <= 4'b0000; else if (en) q <= q + 1; end endmodule
a) 4 bit synchronous up counter with synchronous active LOW reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and asynchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit synchronous Up counter. If the reset signal becomes LOW, the counter resets to 0000. Therefore the reset is active LOW. The reset is synchronous since the counter can be reset only on the positive edge of the clock. If the enable signal becomes HIGH, the counter starts counting up from 0000 to 1111. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 1111 is 0000.
8. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [3:0] q; //output always @ (posedge clk) begin if (!reset) q <= 4'b0000; else if (en) q <= q - 1; end endmodule
a) 4 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active LOW reset and synchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit Down counter. If the reset signal becomes LOW, the counter resets to 0000. So the reset is active LOW. The reset is synchronous since the counter can be reset only on the positive edge of the clock. If the enable signal becomes HIGH, the counter starts counting down from 1111 to 0000. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 0000 is 1111.
9. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [2:0] q; //output always @ (posedge clk) begin if (reset) q <= 3'b000; else if (en) q <= q + 1; end endmodule
a) 2 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 2 bit synchronous down counter with synchronous active HIGH reset and asynchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 3 bit synchronous Up counter. If the reset signal becomes HIGH, the counter resets to 000. Therefore the reset is active HIGH. The reset is synchronous since the counter can reset only on the positive edge of the clock. If the enable signal becomes HIGH, the counter starts counting up from 000 to 111. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 111 is 000.
10. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [2:0] q; //output always @ (posedge clk) begin if (reset) q <= 3'b000; else if (en) q <= q - 1; end endmodule
a) 4 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit Down counter. If the reset signal becomes HIGH, the counter resets to 000. So the reset is active HIGH. The reset is synchronous since the counter will reset can on the positive edge of the clock. If the enable signal becomes HIGH, the counter starts counting down from 111 to 000. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 000 is 111.
11. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [2:0] q; //output always @ (posedge clk or posedge reset) begin if (reset) q <= 3'b000; else if (en) q <= q + 1; end endmodule
a) 2 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 2 bit synchronous down counter with asynchronous active HIGH reset and asynchronous active HIGH enable
c) 3 bit synchronous up counter with asynchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with asynchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 3 bit synchronous Up counter. If the reset signal becomes HIGH, the counter resets to 000. Therefore the reset is active HIGH. The reset is asynchronous since it is independent of the clock. If the enable signal becomes HIGH, the counter starts counting up from 000 to 111. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 111 is 000.
12. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [2:0] q; //output always @ (posedge clk or negedge reset) begin if (!reset) q <= 3'b000; else if (en) q <= q + 1; end endmodule
a) 2 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 2 bit synchronous down counter with asynchronous active HIGH reset and asynchronous active HIGH enable
c) 3 bit synchronous up counter with asynchronous active LOW reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with asynchronous active HIGH reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 3 bit synchronous Up counter. If the reset signal becomes LOW, the counter resets to 000. Therefore the reset is active LOW. The reset is asynchronous since it is independent of the clock. Negative edge triggering is used for the asynchronous active LOW signal. If the enable signal becomes HIGH, the counter starts counting up from 000 to 111. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 111 is 000.
13. What does the following Verilog code synthesize to?
module dut(reset, en, clk, q); input reset; //reset signal input en; //enable signal input clk; //clock signal output reg [2:0] q; //output always @ (posedge clk or negedge reset) begin if (!reset) q <= 3'b000; else if (en) q <= q - 1; end endmodule
a) 4 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
b) 4 bit synchronous down counter with synchronous active HIGH reset and synchronous active HIGH enable
c) 3 bit synchronous up counter with synchronous active HIGH reset and synchronous active HIGH enable
d) 3 bit synchronous down counter with asynchronous active LOW reset and synchronous active HIGH enable
View Answer
Explanation: The above Verilog code would synthesize to a 4 bit Down counter. If the reset signal becomes LOW, the counter resets to 000. Therefore the reset is active LOW. The reset is asynchronous since it is independent of the clock. Negative edge triggering is used for the Asynchronous active LOW signal. If the enable signal becomes HIGH, the counter starts counting down from 111 to 000. Therefore the enable is active HIGH. The enable is synchronous since the counter can be enabled only on the positive edge of the clock. The state after 000 is 111 .
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