Logic Design Questions and Answers – Design of Binary Counters – Set 2

This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Design of Binary Counters – Set 2”.

1. Write the Verilog code for a synchronous 4-bit UP/DOWN Counter. The counter counts upwards if the “up_down” signal is HIGH and downwards if the “up_down” signal is LOW. The output is “q” and the clock signal is “clk”.
a)

```module counter (q, clk, up_down);
output reg [3:0] q;
input up_down, clk;
always @(posedge clk)
begin
if (up_down)
q <= q + 4’b0001;
else
q <= q - 4’b0001;
end
endmodule```

b)

```module counter (q, clk, up_down, reset);
output reg [3:0] q;
input up_down, clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 4'b0000;
else if (!up_down)
q <= q + 4'b0001;
else
q <= q - 4'b0001;
end
endmodule```

c)

```module counter (q, clk, up_down, reset);
output reg [4:0] q;
input up_down, clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 0;
else if (!up_down)
q <= q + 1;
else
q <= q - 1;
end
endmodule```

d)

```module counter (q, clk, up_down, reset);
output reg [4:0] q;
input up_down, clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 0;
else
q <= q + 1;
end
endmodule```
Explanation: If the up_down signal is HIGH, the counter counts upwards. Else if the up_down signal is LOW the counter counts downwards. Since the counter is 4 bit wide, the maximum value is 1111. When the counter is in up counting mode, it counts up from 0000 to 1111. When the counter is in down counting mode, it counts down from 1111 to 0000.

2. Write the Verilog code for a synchronous 4-bit UP/DOWN Counter. The counter counts downwards if the “up_down” signal is HIGH and upwards if the “up_down” signal is LOW. The counter should reset to Zero if the “reset” signal is HIGH. The output is “q” and the clock signal is “clk”.
a)

```module counter (q, clk, up_down);
output reg [3:0] q;
input up_down, clk;
always @(posedge clk)
begin
if (up_down)
q <= q + 4’b0001;
else
q <= q - 4’b0001;
end
endmodule```

b)

```module counter (q, clk, up_down, reset);
output reg [3:0] q;
input up_down, clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 4'b0000;
else if (!up_down)
q <= q + 4'b0001;
else
q <= q - 4'b0001;
end
endmodule```

c)

```module counter (q, clk, up_down, reset);
output reg [4:0] q;
input up_down, clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 0;
else if (!up_down)
q <= q + 1;
else
q <= q - 1;
end
endmodule```

d)

```module counter (q, clk, up_down, reset);
output reg [4:0] q;
input up_down, clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 0;
else
q <= q + 1;
end
endmodule```
Explanation: If the up_down signal is LOW, the counter counts upwards. Else if the up_down signal is HIGH the counter counts downwards. The counter resets to Zero if the reset signal is HIGH.

3. Design a 4-bit synchronous counter with Active LOW load signal called “load” and an Active HIGH reset signal called “reset”. The input data is denoted as “d” and the output is denoted as “q”. The clock signal is “clk”.
a)

```module counter (q, clk, load, reset, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
if (reset)
q <= 4’b0000;
q <= d;
else
q <= q + 4’b0001;
end
endmodule```

b)

```module counter (q, clk, load, reset, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
if (reset)
q <= 4’b0000;
q <= d;
else
q <= q + 4’b0001;
end
endmodule```

c)

```module counter (q, clk, load, reset, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
if (!reset)
q <= 4’b0000;
q <= d;
else
q <= q + 4’b0001;
end
endmodule```

d)

```module counter (q, clk, load, reset, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
if (!reset)
q <= 4’b0000;
q <= d;
else
q <= q + 4’b0001;
end
endmodule```
Explanation: The counter is 4 bit wide and synchronous. Since the load signal is Active LOW, the input data is copied when the load signal becomes LOW. Hence (!load) is used as the condition of the if statement. The reset signal is Active HIGH.

4. Design a 4-bit synchronous counter with an active LOW enable signal called “enable” and an active HIGH load signal called “load”. The input data is denoted as “d” and the output is denoted as “q”. The clock signal is “clk”.
a)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (!enable)
q <= q + 4’b0001;
end
endmodule```

b)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (!enable)
q <= q + 4’b0001;
end
endmodule```

c)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (enable)
q <= q + 4’b0001;
end
endmodule```

d)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (enable)
q <= q + 4’b0001;
end
endmodule```
Explanation: The counter is 4 bit wide and synchronous. The load signal is Active HIGH. If the load signal becomes HIGH, data “d” is loaded into the counter. The enable signal is Active LOW. If the enable signal becomes LOW, the counter starts counting.

5. Design a 4-bit synchronous counter with an active LOW enable signal called “enable” and an active LOW load signal called “load”. The input data is denoted as “d” and the output is denoted as “q”. The clock signal is “clk”.
a)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (!enable)
q <= q + 4’b0001;
end
endmodule```

b)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (!enable)
q <= q + 4’b0001;
end
endmodule```

c)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (enable)
q <= q + 4’b0001;
end
endmodule```

d)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (enable)
q <= q + 4’b0001;
end
endmodule```
Explanation: The counter is 4 bit wide and synchronous. The load signal is Active LOW. If the load signal becomes LOW, data “d” is loaded into the counter. The enable signal is Active LOW. If the enable signal becomes LOW, the counter starts counting.

6. Design a 4-bit synchronous counter with an active HIGH enable signal called “enable” and an active LOW load signal called “load”. The input data is denoted as “d” and the output is denoted as “q”. The clock signal is “clk”.
a)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (!enable)
q <= q + 4’b0001;
end
endmodule```

b)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (!enable)
q <= q + 4’b0001;
end
endmodule```

c)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (enable)
q <= q + 4’b0001;
end
endmodule```

d)

```module counter (q, clk, load, enable, d);
output reg [3:0] q;
input [3:0] d;
always @(posedge clk)
begin
q <= d;
else if (enable)
q <= q + 4’b0001;
end
endmodule```
Explanation: The counter is 4 bit wide and synchronous. The load signal is Active LOW. If the load signal becomes LOW, data “d” is loaded into the counter. The enable signal is Active HIGH. If the enable signal becomes HIGH, the counter starts counting.

7. Write the Verilog code for a 4-bit synchronous UP/DOWN Counter with an Active LOW load signal “load”. The counter counts upwards if the “up_down” signal is HIGH and downwards if the “up_down” signal is LOW. The output is “q” and the clock signal is “clk”. The input data is “d”.
a)

```module counter (q, clk, up_down, d, load);
output reg [3:0] q;
input [3:0] d;
integer direction;
always @(posedge clk)
begin
if (up_down)
direction = 1;
else
direction = -1;
q <= d;
else
q <= q + direction;
end
endmodule```

b)

```module counter (q, clk, up_down, d, load);
output reg [3:0] q;
input [3:0] d;
integer direction;
always @(posedge clk)
begin
if (up_down)
direction = 1;
else
direction = -1;
q <= d;
else
q <= q - direction;
end
endmodule```

c)

```module counter (q, clk, up_down, d, load);
output reg [3:0] q;
input [3:0] d;
integer direction;
always @(posedge clk)
begin
if (!up_down)
direction = 1;
else
direction = -1;
q <= d;
else
q <= q + direction;
end
endmodule```

d)

```module counter (q, clk, up_down, d, load);
output reg [3:0] q;
input [3:0] d;
integer direction;
always @(posedge clk)
begin
if (up_down)
direction = 1;
else
direction = -1;
q <= d;
else
q <= q + 4’b0001;
end
endmodule```
Explanation: The 4-bit synchronous UP/DOWN counter has an active LOW load signal. If the load signal becomes LOW, data is loaded into the counter. Else the counter counts upwards or downwards depending on the state of the “up_down” signal. If the up_down signal is HIGH, it counts upwards, If the up_down signal is LOW, it counts backwards. This is done by setting an integer “direction’ as 1 if up_down is HIGH and as -1 if up_down is LOW.

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